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Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
irrelevant, but add a new test for the new, improved functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4194,10 +4194,6 @@ static SDValue PerformMULCombine(SDNode *N,
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if (Subtarget->isThumb1Only())
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return SDValue();
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if (DAG.getMachineFunction().
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getFunction()->hasFnAttr(Attribute::OptimizeForSize))
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return SDValue();
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if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
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return SDValue();
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@ -1,15 +0,0 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
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define void @b(i32 %x) nounwind optsize {
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entry:
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; CHECK: b
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; CHECK: mov r2, sp
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; CHECK: mls r0, r0, r1, r2
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; CHECK: mov sp, r0
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%0 = mul i32 %x, 24 ; <i32> [#uses=1]
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%vla = alloca i8, i32 %0, align 1 ; <i8*> [#uses=1]
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call arm_aapcscc void @a(i8* %vla) nounwind optsize
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ret void
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}
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declare void @a(i8*) optsize
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18
test/CodeGen/thumb2-mul.ll
Normal file
18
test/CodeGen/thumb2-mul.ll
Normal file
@ -0,0 +1,18 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
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%struct.CMPoint = type { %struct.Point, float, float, [5 x float] }
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%struct.Point = type { float, float }
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define %struct.CMPoint* @t1(i32 %i, i32 %j, i32 %n, %struct.CMPoint* %thePoints) nounwind readnone ssp {
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entry:
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; CHECK: mla r0, r2, r0, r1
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; CHECK: add.w r0, r0, r0, lsl #3
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; CHECL: add.w r0, r3, r0, lsl #2
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%mul = mul i32 %n, %i
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%add = add i32 %mul, %j
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%0 = ptrtoint %struct.CMPoint* %thePoints to i32
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%mul5 = mul i32 %add, 36
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%add6 = add i32 %mul5, %0
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%1 = inttoptr i32 %add6 to %struct.CMPoint*
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ret %struct.CMPoint* %1
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}
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