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we can't do this directly in lowering, so we need this case

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24951 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2005-12-22 07:14:45 +00:00
parent 3d821e26a1
commit 8617f3cf14
1 changed files with 8 additions and 0 deletions
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8
lib/Target/IA64/IA64ISelDAGToDAG.cpp
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@ -343,6 +343,14 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
case ISD::Register: return Op; // XXX: this is a hack, tblgen one day?
case IA64ISD::GETFD: {
SDOperand Input = Select(N->getOperand(0));
SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, MVT::Flag, Input);
CodeGenMap[Op.getValue(0)] = Result;
CodeGenMap[Op.getValue(1)] = Result.getValue(1);
return Result.getValue(Op.ResNo);
}
case ISD::CALL:
case ISD::TAILCALL: { {
// FIXME: This is a workaround for a bug in tblgen.