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we can't do this directly in lowering, so we need this case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24951 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -343,6 +343,14 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
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case ISD::Register: return Op; // XXX: this is a hack, tblgen one day?
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case IA64ISD::GETFD: {
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SDOperand Input = Select(N->getOperand(0));
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SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, MVT::Flag, Input);
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CodeGenMap[Op.getValue(0)] = Result;
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CodeGenMap[Op.getValue(1)] = Result.getValue(1);
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return Result.getValue(Op.ResNo);
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}
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case ISD::CALL:
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case ISD::TAILCALL: { {
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// FIXME: This is a workaround for a bug in tblgen.
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