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Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-10-22 06:48:32 +00:00
parent faf93aa233
commit 87689d3b70
2 changed files with 5 additions and 6 deletions
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8
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -103,18 +103,16 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
PM.add(createARMLoadStoreOptimizationPass());
PM.add(createIfConverterPass());
}
return true;
}
bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createIfConverterPass());
if (Subtarget.isThumb2()) {
PM.add(createThumb2ITBlockPass());
PM.add(createThumb2SizeReductionPass());

3
test/CodeGen/ARM/ifcvt5.ll
View File

@ -11,7 +11,8 @@ entry:
define void @t1(i32 %a, i32 %b) {
; CHECK: t1:
; CHECK: ldmltfd sp!, {r7, pc}
; CHECK: movge
; CHECK: blge _foo
entry:
%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock