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Minor postra scheduler cleanup. It could result in more precise antidependence latency on ARM in exceedingly rare cases.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147594 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-01-05 02:52:11 +00:00
parent 397ae210ce
commit 877ae2ee17
1 changed files with 19 additions and 25 deletions
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44
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -260,9 +260,6 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
std::vector<SUnit *> &UseList = Uses[Reg];
// Defs are push in the order they are visited and never reordered.
std::vector<SUnit *> &DefList = Defs[Reg];
// Optionally add output and anti dependencies. For anti
// dependencies we use a latency of 0 because for a multi-issue
// target we want to allow the defining instruction to issue
@ -271,36 +268,33 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
// there's no cost for reusing registers.
SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
unsigned AOLatency = (Kind == SDep::Anti) ? 0 : 1;
for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
SUnit *DefSU = DefList[i];
if (DefSU == &ExitSU)
continue;
if (DefSU != SU &&
(Kind != SDep::Output || !MO.isDead() ||
!DefSU->getInstr()->registerDefIsDead(Reg))) {
if (Kind == SDep::Anti)
DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg));
else {
unsigned AOLat = TII->getOutputLatency(InstrItins, MI, j,
DefSU->getInstr());
DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg));
}
}
}
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
std::vector<SUnit *> &MemDefList = Defs[*Alias];
for (unsigned i = 0, e = MemDefList.size(); i != e; ++i) {
SUnit *DefSU = MemDefList[i];
for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) {
std::vector<SUnit *> &DefList = Defs[*Alias];
for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
SUnit *DefSU = DefList[i];
if (DefSU == &ExitSU)
continue;
if (DefSU != SU &&
(Kind != SDep::Output || !MO.isDead() ||
!DefSU->getInstr()->registerDefIsDead(*Alias)))
DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias));
!DefSU->getInstr()->registerDefIsDead(*Alias))) {
if (Kind == SDep::Anti)
DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
else {
unsigned AOLat = TII->getOutputLatency(InstrItins, MI, j,
DefSU->getInstr());
DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
}
}
}
}
// Retrieve the UseList to add data dependencies and update uses.
std::vector<SUnit *> &UseList = Uses[Reg];
if (MO.isDef()) {
// Update DefList. Defs are pushed in the order they are visited and
// never reordered.
std::vector<SUnit *> &DefList = Defs[Reg];
// Add any data dependencies.
unsigned DataLatency = SU->Latency;
for (unsigned i = 0, e = UseList.size(); i != e; ++i) {