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https://github.com/c64scene-ar/llvm-6502.git
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Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn subeq r0, r1, #1 addne r0, r1, #1 into sub r0, r1, #1 addne r0, r1, #1 For targets where conditional instructions are always executed, this may be beneficial. It may remove pseudo anti-dependency in out-of-order execution CPUs. e.g. op r1, ... str r1, [r10] ; end-of-life of r1 as div result cmp r0, #65 movne r1, #44 ; raw dependency on previous r1 moveq r1, #12 If movne is unpredicated, then op r1, ... str r1, [r10] cmp r0, #65 mov r1, #44 ; r1 written unconditionally moveq r1, #12 Both mov and moveq are no longer depdendent on the first instruction. This gives the out-of-order execution engine more freedom to reorder them. This has passed entire LLVM test suite. But it has not been enabled for any ARM variant pending more performance evaluation. rdar://8951196 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146914 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
638905d90c
commit
8787c5f24e
@ -353,6 +353,22 @@ public:
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return false;
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}
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/// isProfitableToUnpredicate - Return true if it's profitable to unpredicate
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/// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
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/// exclusive predicates.
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/// e.g.
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/// subeq r0, r1, #1
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/// addne r0, r1, #1
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/// =>
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/// sub r0, r1, #1
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/// addne r0, r1, #1
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///
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/// This may be profitable is conditional instructions are always executed.
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virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const {
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return false;
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}
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/// copyPhysReg - Emit instructions to copy a pair of physical registers.
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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@ -62,6 +62,7 @@ STATISTIC(NumTriangleFRev, "Number of triangle (F/R) if-conversions performed");
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STATISTIC(NumDiamonds, "Number of diamond if-conversions performed");
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STATISTIC(NumIfConvBBs, "Number of if-converted blocks");
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STATISTIC(NumDupBBs, "Number of duplicated blocks");
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STATISTIC(NumUnpred, "Number of true blocks of diamonds unpredicated");
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namespace {
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class IfConverter : public MachineFunctionPass {
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@ -195,7 +196,8 @@ namespace {
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void PredicateBlock(BBInfo &BBI,
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MachineBasicBlock::iterator E,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallSet<unsigned, 4> &Redefs);
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SmallSet<unsigned, 4> &Redefs,
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SmallSet<unsigned, 4> *LaterRedefs = 0);
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void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallSet<unsigned, 4> &Redefs,
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@ -1280,7 +1282,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1);
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BBI2->BB->erase(BBI2->BB->begin(), DI2);
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// Predicate the 'true' block after removing its branch.
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// Remove branch from 'true' block and remove duplicated instructions.
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BBI1->NonPredSize -= TII->RemoveBranch(*BBI1->BB);
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DI1 = BBI1->BB->end();
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for (unsigned i = 0; i != NumDups2; ) {
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@ -1293,9 +1295,8 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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++i;
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}
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BBI1->BB->erase(DI1, BBI1->BB->end());
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PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, Redefs);
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// Predicate the 'false' block.
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// Remove 'false' block branch and find the last instruction to predicate.
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BBI2->NonPredSize -= TII->RemoveBranch(*BBI2->BB);
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DI2 = BBI2->BB->end();
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while (NumDups2 != 0) {
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@ -1307,6 +1308,55 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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if (!DI2->isDebugValue())
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--NumDups2;
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}
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// Remember which registers would later be defined by the false block.
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// This allows us not to predicate instructions in the true block that would
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// later be re-defined. That is, rather than
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// subeq r0, r1, #1
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// addne r0, r1, #1
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// generate:
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// sub r0, r1, #1
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// addne r0, r1, #1
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SmallSet<unsigned, 4> RedefsByFalse;
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SmallSet<unsigned, 4> ExtUses;
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if (TII->isProfitableToUnpredicate(*BBI1->BB, *BBI2->BB)) {
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for (MachineBasicBlock::iterator FI = BBI2->BB->begin(); FI != DI2; ++FI) {
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if (FI->isDebugValue())
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continue;
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SmallVector<unsigned, 4> Defs;
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for (unsigned i = 0, e = FI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = FI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (MO.isDef()) {
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Defs.push_back(Reg);
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} else if (!RedefsByFalse.count(Reg)) {
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// These are defined before ctrl flow reach the 'false' instructions.
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// They cannot be modified by the 'true' instructions.
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ExtUses.insert(Reg);
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for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
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ExtUses.insert(*SR);
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}
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}
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for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
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unsigned Reg = Defs[i];
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if (!ExtUses.count(Reg)) {
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RedefsByFalse.insert(Reg);
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for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
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RedefsByFalse.insert(*SR);
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}
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}
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}
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}
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// Predicate the 'true' block.
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PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, Redefs, &RedefsByFalse);
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// Predicate the 'false' block.
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PredicateBlock(*BBI2, DI2, *Cond2, Redefs);
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// Merge the true block into the entry of the diamond.
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@ -1355,15 +1405,49 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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return true;
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}
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static bool MaySpeculate(const MachineInstr *MI,
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SmallSet<unsigned, 4> &LaterRedefs,
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const TargetInstrInfo *TII) {
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bool SawStore = true;
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if (!MI->isSafeToMove(TII, 0, SawStore))
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return false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (MO.isDef() && !LaterRedefs.count(Reg))
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return false;
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}
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return true;
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}
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/// PredicateBlock - Predicate instructions from the start of the block to the
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/// specified end with the specified condition.
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void IfConverter::PredicateBlock(BBInfo &BBI,
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MachineBasicBlock::iterator E,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallSet<unsigned, 4> &Redefs) {
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SmallSet<unsigned, 4> &Redefs,
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SmallSet<unsigned, 4> *LaterRedefs) {
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bool AnyUnpred = false;
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bool MaySpec = LaterRedefs != 0;
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for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) {
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if (I->isDebugValue() || TII->isPredicated(I))
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continue;
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// It may be possible not to predicate an instruction if it's the 'true'
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// side of a diamond and the 'false' side may re-define the instruction's
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// defs.
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if (MaySpec && MaySpeculate(I, *LaterRedefs, TII)) {
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AnyUnpred = true;
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continue;
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}
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// If any instruction is predicated, then every instruction after it must
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// be predicated.
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MaySpec = false;
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if (!TII->PredicateInstruction(I, Cond)) {
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#ifndef NDEBUG
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dbgs() << "Unable to predicate " << *I << "!\n";
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@ -1382,6 +1466,8 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
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BBI.NonPredSize = 0;
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++NumIfConvBBs;
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if (AnyUnpred)
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++NumUnpred;
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}
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/// CopyAndPredicateBlock - Copy and predicate instructions from source BB to
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