6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-19 03:29:22 +00:00
Code Issues Projects Releases Wiki Activity

disentangle FP from INT versions of div/mul

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-09-28 22:50:24 +00:00
parent 4a7de219b4
commit 88add100b3
1 changed files with 16 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -820,7 +820,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
Select(N->getOperand(1))); Select(N->getOperand(1)));
return SDOperand(N, 0); return SDOperand(N, 0);
} }
case ISD::FMUL:
case ISD::MUL: { case ISD::MUL: {
unsigned Imm, Opc; unsigned Imm, Opc;
if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) { if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
@ -828,18 +827,17 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
Select(N->getOperand(0)), getI32Imm(Lo16(Imm))); Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
return SDOperand(N, 0); return SDOperand(N, 0);
} }
switch (N->getValueType(0)) { CurDAG->SelectNodeTo(N, PPC::MULLW, MVT::i32, Select(N->getOperand(0)),
default: assert(0 && "Unhandled multiply type!");
case MVT::i32: Opc = PPC::MULLW; break;
case MVT::f32: Opc = PPC::FMULS; break;
case MVT::f64: Opc = PPC::FMUL; break;
}
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
Select(N->getOperand(1))); Select(N->getOperand(1)));
return SDOperand(N, 0); return SDOperand(N, 0);
} }
case ISD::SDIV: case ISD::FMUL: {
case ISD::FDIV: { unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FMULS : PPC::FMUL;
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
Select(N->getOperand(1)));
return SDOperand(N, 0);
}
case ISD::SDIV: {
unsigned Imm; unsigned Imm;
if (isIntImmediate(N->getOperand(1), Imm)) { if (isIntImmediate(N->getOperand(1), Imm)) {
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
@ -869,17 +867,17 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
} }
} }
unsigned Opc; CurDAG->SelectNodeTo(N, PPC::DIVW, MVT::i32, Select(N->getOperand(0)),
switch (N->getValueType(0)) {
default: assert(0 && "Unknown type to ISD::SDIV");
case MVT::i32: Opc = PPC::DIVW; break;
case MVT::f32: Opc = PPC::FDIVS; break;
case MVT::f64: Opc = PPC::FDIV; break;
}
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
Select(N->getOperand(1))); Select(N->getOperand(1)));
return SDOperand(N, 0); return SDOperand(N, 0);
} }
case ISD::FDIV: {
unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FDIVS : PPC::FDIV;
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
Select(N->getOperand(1)));
return SDOperand(N, 0);
}
case ISD::UDIV: { case ISD::UDIV: {
// If this is a divide by constant, we can emit code using some magic // If this is a divide by constant, we can emit code using some magic
// constants to implement it as a multiply instead. // constants to implement it as a multiply instead.