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When converting virtual registers to immediate constants, change the opcode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6452 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2003-05-30 20:36:27 +00:00
parent da3a8b19ce
commit 88ba25444c
2 changed files with 28 additions and 0 deletions
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14
lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
View File

@ -16,6 +16,7 @@
#include "llvm/Constants.h"
#include "llvm/BasicBlock.h"
#include "llvm/DerivedTypes.h"
#include "../../Target/Sparc/SparcInstrSelectionSupport.h"
using std::vector;
//*************************** Local Functions ******************************/
@ -186,6 +187,12 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
immedValue);
if (opType == MachineOperand::MO_VirtualRegister)
constantThatMustBeLoaded = true;
else {
// The optype has changed from being a register to an immediate
// This means we need to change the opcode, e.g. ADDr -> ADDi
unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
minstr->setOpcode(newOpcode);
}
}
}
else
@ -213,6 +220,13 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
: (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
}
else
{
// The optype has changed from being a register to an immediate
// This means we need to change the opcode, e.g. ADDr -> ADDi
unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
minstr->setOpcode(newOpcode);
}
}
if (opType == MachineOperand::MO_MachineRegister)

14
lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
View File

@ -16,6 +16,7 @@
#include "llvm/Constants.h"
#include "llvm/BasicBlock.h"
#include "llvm/DerivedTypes.h"
#include "../../Target/Sparc/SparcInstrSelectionSupport.h"
using std::vector;
//*************************** Local Functions ******************************/
@ -186,6 +187,12 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
immedValue);
if (opType == MachineOperand::MO_VirtualRegister)
constantThatMustBeLoaded = true;
else {
// The optype has changed from being a register to an immediate
// This means we need to change the opcode, e.g. ADDr -> ADDi
unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
minstr->setOpcode(newOpcode);
}
}
}
else
@ -213,6 +220,13 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
: (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
}
else
{
// The optype has changed from being a register to an immediate
// This means we need to change the opcode, e.g. ADDr -> ADDi
unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
minstr->setOpcode(newOpcode);
}
}
if (opType == MachineOperand::MO_MachineRegister)