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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Adding reg-reg indexed load forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224997 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
7d099f9e6a
commit
88e5659aaf
@ -50,6 +50,8 @@ def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">;
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//===----------------------------------------------------------------------===//
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// Classes used for relation maps.
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//===----------------------------------------------------------------------===//
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class ImmRegShl;
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// PredRel - Filter class used to relate non-predicated instructions with their
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// predicated forms.
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class PredRel;
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@ -180,6 +182,14 @@ def getRegForm : InstrMapping {
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let ValueCols = [["reg"]];
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}
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def getRegShlForm : InstrMapping {
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let FilterClass = "ImmRegShl";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["InputType"];
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let KeyCol = ["imm"];
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let ValueCols = [["reg"]];
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}
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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@ -1351,31 +1351,31 @@ isConditionalLoad (const MachineInstr* MI) const {
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case Hexagon::L2_ploadrubt_io:
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case Hexagon::L2_ploadrubf_io:
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return true;
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case Hexagon::L2_ploadrdt_pi :
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case Hexagon::L2_ploadrdf_pi :
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case Hexagon::L2_ploadrit_pi :
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case Hexagon::L2_ploadrif_pi :
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case Hexagon::L2_ploadrht_pi :
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case Hexagon::L2_ploadrhf_pi :
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case Hexagon::L2_ploadrbt_pi :
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case Hexagon::L2_ploadrbf_pi :
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case Hexagon::L2_ploadruht_pi :
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case Hexagon::L2_ploadruhf_pi :
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case Hexagon::L2_ploadrubt_pi :
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case Hexagon::L2_ploadrubf_pi :
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case Hexagon::L2_ploadrdt_pi:
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case Hexagon::L2_ploadrdf_pi:
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case Hexagon::L2_ploadrit_pi:
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case Hexagon::L2_ploadrif_pi:
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case Hexagon::L2_ploadrht_pi:
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case Hexagon::L2_ploadrhf_pi:
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case Hexagon::L2_ploadrbt_pi:
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case Hexagon::L2_ploadrbf_pi:
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case Hexagon::L2_ploadruht_pi:
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case Hexagon::L2_ploadruhf_pi:
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case Hexagon::L2_ploadrubt_pi:
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case Hexagon::L2_ploadrubf_pi:
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return QRI.Subtarget.hasV4TOps();
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case Hexagon::LDrid_indexed_shl_cPt_V4 :
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case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
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case Hexagon::LDrib_indexed_shl_cPt_V4 :
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case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
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case Hexagon::LDriub_indexed_shl_cPt_V4 :
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case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
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case Hexagon::LDrih_indexed_shl_cPt_V4 :
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case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
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case Hexagon::LDriuh_indexed_shl_cPt_V4 :
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case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
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case Hexagon::LDriw_indexed_shl_cPt_V4 :
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case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
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case Hexagon::L4_ploadrdt_rr:
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case Hexagon::L4_ploadrdf_rr:
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case Hexagon::L4_ploadrbt_rr:
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case Hexagon::L4_ploadrbf_rr:
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case Hexagon::L4_ploadrubt_rr:
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case Hexagon::L4_ploadrubf_rr:
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case Hexagon::L4_ploadrht_rr:
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case Hexagon::L4_ploadrhf_rr:
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case Hexagon::L4_ploadruht_rr:
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case Hexagon::L4_ploadruhf_rr:
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case Hexagon::L4_ploadrit_rr:
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case Hexagon::L4_ploadrif_rr:
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return QRI.Subtarget.hasV4TOps();
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}
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}
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@ -342,112 +342,152 @@ def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
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def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
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def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
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//===----------------------------------------------------------------------===//
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// Template classes for the non-predicated load instructions with
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// base + register offset addressing mode
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//===----------------------------------------------------------------------===//
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class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
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LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
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"$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
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[], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
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bits<5> dst;
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bits<5> src1;
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bits<5> src2;
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bits<2> u2;
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let IClass = 0b0011;
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let Inst{27-24} = 0b1010;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = src1;
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let Inst{12-8} = src2;
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let Inst{13} = u2{1};
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let Inst{7} = u2{0};
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let Inst{4-0} = dst;
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}
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//===----------------------------------------------------------------------===//
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// Template classes for the predicated load instructions with
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// base + register offset addressing mode
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//===----------------------------------------------------------------------===//
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let isPredicated = 1 in
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class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
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bit isNot, bit isPredNew>:
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LDInst <(outs RC:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
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[], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
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bits<5> dst;
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bits<2> src1;
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bits<5> src2;
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bits<5> src3;
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bits<2> u2;
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let isPredicatedFalse = isNot;
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let isPredicatedNew = isPredNew;
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let IClass = 0b0011;
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let Inst{27-26} = 0b00;
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let Inst{25} = isPredNew;
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let Inst{24} = isNot;
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let Inst{23-21} = MajOp;
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let Inst{20-16} = src2;
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let Inst{12-8} = src3;
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let Inst{13} = u2{1};
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let Inst{7} = u2{0};
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let Inst{6-5} = src1;
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let Inst{4-0} = dst;
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}
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//===----------------------------------------------------------------------===//
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// multiclass for load instructions with base + register offset
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// addressing mode
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multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
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bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME : LDInst2<(outs RC:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
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[]>, Requires<[HasV4T]>;
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}
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multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
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}
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}
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let hasSideEffects = 0 in
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multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, addrMode = BaseRegOffset in
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multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
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bits<3> MajOp > {
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let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
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InputType = "reg" in {
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let isPredicable = 1 in
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def NAME#_V4 : LDInst2<(outs RC:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
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"$dst = "#mnemonic#"($src1+$src2<<#$offset)",
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[]>, Requires<[HasV4T]>;
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def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
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let isPredicated = 1 in {
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defm Pt_V4 : ld_idxd_shl_pred<mnemonic, RC, 0 >;
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defm NotPt_V4 : ld_idxd_shl_pred<mnemonic, RC, 1>;
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}
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// Predicated
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def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
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def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
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// Predicated new
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def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
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def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
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}
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}
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let addrMode = BaseRegOffset in {
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let accessSize = ByteAccess in {
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defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>,
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AddrModeRel;
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defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>,
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AddrModeRel;
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}
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let accessSize = HalfWordAccess in {
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defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel;
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defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>,
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AddrModeRel;
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}
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let accessSize = WordAccess in
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defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel;
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let accessSize = DoubleWordAccess in
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defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>,
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AddrModeRel;
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let hasNewValue = 1, accessSize = ByteAccess, isCodeGenOnly = 0 in {
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defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
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defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
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}
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let hasNewValue = 1, accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
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defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
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defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
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}
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let hasNewValue = 1, accessSize = WordAccess, isCodeGenOnly = 0 in
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defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
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let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
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defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
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// 'def pats' for load instructions with base + register offset and non-zero
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// immediate value. Immediate value is used to left-shift the second
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// register operand.
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let AddedComplexity = 40 in {
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def : Pat <(i32 (sextloadi8 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDrib_indexed_shl_V4 IntRegs:$src1,
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(L4_loadrb_rr IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (zextloadi8 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDriub_indexed_shl_V4 IntRegs:$src1,
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(L4_loadrub_rr IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDriub_indexed_shl_V4 IntRegs:$src1,
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(L4_loadrub_rr IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDrih_indexed_shl_V4 IntRegs:$src1,
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(L4_loadrh_rr IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDriuh_indexed_shl_V4 IntRegs:$src1,
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(L4_loadruh_rr IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDriuh_indexed_shl_V4 IntRegs:$src1,
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(L4_loadruh_rr IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (load (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDriw_indexed_shl_V4 IntRegs:$src1,
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(L4_loadri_rr IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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def : Pat <(i64 (load (add IntRegs:$src1,
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(shl IntRegs:$src2, u2ImmPred:$offset)))),
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(LDrid_indexed_shl_V4 IntRegs:$src1,
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(L4_loadrd_rr IntRegs:$src1,
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IntRegs:$src2, u2ImmPred:$offset)>,
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Requires<[HasV4T]>;
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}
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@ -457,35 +497,35 @@ def : Pat <(i64 (load (add IntRegs:$src1,
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// zero immediate value.
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let AddedComplexity = 10 in {
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def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
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(LDrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
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(L4_loadrd_rr IntRegs:$src1, IntRegs:$src2, 0)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
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(LDrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
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(L4_loadrb_rr IntRegs:$src1, IntRegs:$src2, 0)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
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(LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
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(L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
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(LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
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(L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
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(LDrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
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(L4_loadrh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
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(LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
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(L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
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(LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
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(L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>,
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Requires<[HasV4T]>;
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def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
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(LDriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
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(L4_loadri_rr IntRegs:$src1, IntRegs:$src2, 0)>,
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Requires<[HasV4T]>;
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}
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@ -1,7 +1,7 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: r{{[0-9]+}} = CONST32(#.LJTI{{[0-9]+_[0-9]+}})
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; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+<<#[0-9]+}})
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; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}} + r{{[0-9]+<<#[0-9]+}})
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; CHECK: jumpr r{{[0-9]+}}
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define void @main() #0 {
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@ -4,7 +4,7 @@
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; load word
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define i32 @load_w(i32* nocapture %a, i32 %n) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
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entry:
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%tmp = shl i32 %n, 4
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%scevgep9 = getelementptr i32* %a, i32 %tmp
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@ -15,7 +15,7 @@ entry:
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; load unsigned half word
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define i16 @load_uh(i16* nocapture %a, i32 %n) nounwind {
|
||||
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
|
||||
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
|
||||
entry:
|
||||
%tmp = shl i32 %n, 4
|
||||
%scevgep9 = getelementptr i16* %a, i32 %tmp
|
||||
@ -26,7 +26,7 @@ entry:
|
||||
; load signed half word
|
||||
|
||||
define i32 @load_h(i16* nocapture %a, i32 %n) nounwind {
|
||||
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
|
||||
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
|
||||
entry:
|
||||
%tmp = shl i32 %n, 4
|
||||
%scevgep9 = getelementptr i16* %a, i32 %tmp
|
||||
@ -38,7 +38,7 @@ entry:
|
||||
; load unsigned byte
|
||||
|
||||
define i8 @load_ub(i8* nocapture %a, i32 %n) nounwind {
|
||||
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
|
||||
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
|
||||
entry:
|
||||
%tmp = shl i32 %n, 4
|
||||
%scevgep9 = getelementptr i8* %a, i32 %tmp
|
||||
@ -49,7 +49,7 @@ entry:
|
||||
; load signed byte
|
||||
|
||||
define i32 @foo_2(i8* nocapture %a, i32 %n) nounwind {
|
||||
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
|
||||
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
|
||||
entry:
|
||||
%tmp = shl i32 %n, 4
|
||||
%scevgep9 = getelementptr i8* %a, i32 %tmp
|
||||
@ -61,7 +61,7 @@ entry:
|
||||
; load doubleword
|
||||
|
||||
define i64 @load_d(i64* nocapture %a, i32 %n) nounwind {
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
|
||||
entry:
|
||||
%tmp = shl i32 %n, 4
|
||||
%scevgep9 = getelementptr i64* %a, i32 %tmp
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
|
||||
|
||||
0x70 0xd8 0xd5 0x41
|
||||
# CHECK: if (p3) r17:16 = memd(r21 + #24)
|
||||
0x90 0xff 0xd5 0x3a
|
||||
# CHECK: r17:16 = memd(r21 + r31<<#3)
|
||||
0xb0 0xe0 0xd5 0x99
|
||||
# CHECK: r17:16 = memd(r21 ++ #40:circ(m1))
|
||||
0x10 0xe2 0xd5 0x99
|
||||
@ -12,6 +12,18 @@
|
||||
# CHECK: r17:16 = memd(r21++m1)
|
||||
0x10 0xe0 0xd5 0x9f
|
||||
# CHECK: r17:16 = memd(r21 ++ m1:brev)
|
||||
0xf0 0xff 0xd5 0x30
|
||||
# CHECK: if (p3) r17:16 = memd(r21+r31<<#3)
|
||||
0xf0 0xff 0xd5 0x31
|
||||
# CHECK: if (!p3) r17:16 = memd(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf0 0xff 0xd5 0x32
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (p3.new) r17:16 = memd(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf0 0xff 0xd5 0x33
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21+r31<<#3)
|
||||
0x70 0xd8 0xd5 0x41
|
||||
# CHECK: if (p3) r17:16 = memd(r21 + #24)
|
||||
0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x43
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (p3.new) r17:16 = memd(r21 + #24)
|
||||
@ -31,6 +43,8 @@
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21++#40)
|
||||
|
||||
0x91 0xff 0x15 0x3a
|
||||
# CHECK: r17 = memb(r21 + r31<<#3)
|
||||
0xf1 0xc3 0x15 0x91
|
||||
# CHECK: r17 = memb(r21 + #31)
|
||||
0xb1 0xe0 0x15 0x99
|
||||
@ -43,6 +57,16 @@
|
||||
# CHECK: r17 = memb(r21++m1)
|
||||
0x11 0xe0 0x15 0x9f
|
||||
# CHECK: r17 = memb(r21 ++ m1:brev)
|
||||
0xf1 0xff 0x15 0x30
|
||||
# CHECK: if (p3) r17 = memb(r21+r31<<#3)
|
||||
0xf1 0xff 0x15 0x31
|
||||
# CHECK: if (!p3) r17 = memb(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0x32
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (p3.new) r17 = memb(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0x33
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17 = memb(r21+r31<<#3)
|
||||
0x91 0xdd 0x15 0x41
|
||||
# CHECK: if (p3) r17 = memb(r21 + #44)
|
||||
0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x43
|
||||
@ -64,6 +88,8 @@
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)
|
||||
|
||||
0x91 0xff 0x55 0x3a
|
||||
# CHECK: r17 = memh(r21 + r31<<#3)
|
||||
0xf1 0xc3 0x55 0x91
|
||||
# CHECK: r17 = memh(r21 + #62)
|
||||
0xb1 0xe0 0x55 0x99
|
||||
@ -76,6 +102,16 @@
|
||||
# CHECK: r17 = memh(r21++m1)
|
||||
0x11 0xe0 0x55 0x9f
|
||||
# CHECK: r17 = memh(r21 ++ m1:brev)
|
||||
0xf1 0xff 0x55 0x30
|
||||
# CHECK: if (p3) r17 = memh(r21+r31<<#3)
|
||||
0xf1 0xff 0x55 0x31
|
||||
# CHECK: if (!p3) r17 = memh(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xff 0x55 0x32
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (p3.new) r17 = memh(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xff 0x55 0x33
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17 = memh(r21+r31<<#3)
|
||||
0xb1 0xe6 0x55 0x9b
|
||||
# CHECK: if (p3) r17 = memh(r21++#10)
|
||||
0xb1 0xee 0x55 0x9b
|
||||
@ -87,6 +123,8 @@
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17 = memh(r21++#10)
|
||||
|
||||
0x91 0xff 0x35 0x3a
|
||||
# CHECK: r17 = memub(r21 + r31<<#3)
|
||||
0xf1 0xc3 0x35 0x91
|
||||
# CHECK: r17 = memub(r21 + #31)
|
||||
0xb1 0xe0 0x35 0x99
|
||||
@ -99,6 +137,16 @@
|
||||
# CHECK: r17 = memub(r21++m1)
|
||||
0x11 0xe0 0x35 0x9f
|
||||
# CHECK: r17 = memub(r21 ++ m1:brev)
|
||||
0xf1 0xff 0x35 0x30
|
||||
# CHECK: if (p3) r17 = memub(r21+r31<<#3)
|
||||
0xf1 0xff 0x35 0x31
|
||||
# CHECK: if (!p3) r17 = memub(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0x32
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (p3.new) r17 = memub(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0x33
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17 = memub(r21+r31<<#3)
|
||||
0xf1 0xdb 0x35 0x41
|
||||
# CHECK: if (p3) r17 = memub(r21 + #31)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x43
|
||||
@ -120,6 +168,8 @@
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17 = memub(r21++#5)
|
||||
|
||||
0x91 0xff 0x75 0x3a
|
||||
# CHECK: r17 = memuh(r21 + r31<<#3)
|
||||
0xb1 0xc2 0x75 0x91
|
||||
# CHECK: r17 = memuh(r21 + #42)
|
||||
0xb1 0xe0 0x75 0x99
|
||||
@ -132,6 +182,16 @@
|
||||
# CHECK: r17 = memuh(r21++m1)
|
||||
0x11 0xe0 0x75 0x9f
|
||||
# CHECK: r17 = memuh(r21 ++ m1:brev)
|
||||
0xf1 0xff 0x75 0x30
|
||||
# CHECK: if (p3) r17 = memuh(r21+r31<<#3)
|
||||
0xf1 0xff 0x75 0x31
|
||||
# CHECK: if (!p3) r17 = memuh(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xff 0x75 0x32
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (p3.new) r17 = memuh(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xff 0x75 0x33
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17 = memuh(r21+r31<<#3)
|
||||
0xb1 0xda 0x75 0x41
|
||||
# CHECK: if (p3) r17 = memuh(r21 + #42)
|
||||
0xb1 0xda 0x75 0x45
|
||||
@ -153,6 +213,8 @@
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17 = memuh(r21++#10)
|
||||
|
||||
0x91 0xff 0x95 0x3a
|
||||
# CHECK: r17 = memw(r21 + r31<<#3)
|
||||
0xb1 0xc2 0x95 0x91
|
||||
# CHECK: r17 = memw(r21 + #84)
|
||||
0xb1 0xe0 0x95 0x99
|
||||
@ -165,6 +227,16 @@
|
||||
# CHECK: r17 = memw(r21++m1)
|
||||
0x11 0xe0 0x95 0x9f
|
||||
# CHECK: r17 = memw(r21 ++ m1:brev)
|
||||
0xf1 0xff 0x95 0x30
|
||||
# CHECK: if (p3) r17 = memw(r21+r31<<#3)
|
||||
0xf1 0xff 0x95 0x31
|
||||
# CHECK: if (!p3) r17 = memw(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xff 0x95 0x32
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (p3.new) r17 = memw(r21+r31<<#3)
|
||||
0x03 0x40 0x45 0x85 0xf1 0xff 0x95 0x33
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) r17 = memw(r21+r31<<#3)
|
||||
0xb1 0xda 0x95 0x41
|
||||
# CHECK: if (p3) r17 = memw(r21 + #84)
|
||||
0xb1 0xda 0x95 0x45
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user