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Fix grammar / missing words

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192380 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2013-10-10 18:47:35 +00:00
parent b8e48a636e
commit 89dedc1b65
1 changed files with 3 additions and 2 deletions
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5
include/llvm/Target/TargetOpcodes.h
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@ -69,8 +69,9 @@ namespace TargetOpcode {
DBG_VALUE = 11,
/// REG_SEQUENCE - This variadic instruction is used to form a register that
/// represent a consecutive sequence of sub-registers. It's used as register
/// coalescing / allocation aid and must be eliminated before code emission.
/// represents a consecutive sequence of sub-registers. It's used as a
/// register coalescing / allocation aid and must be eliminated before code
/// emission.
// In SDNode form, the first operand encodes the register class created by
// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
// pair. Once it has been lowered to a MachineInstr, the regclass operand