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Re-introduce the 8-bit subreg zext-inreg patterns for x86-32,

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this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54418 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-08-06 18:27:21 +00:00
parent 4ce9627e97
commit 8a1510d192
4 changed files with 25 additions and 34 deletions
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6
lib/Target/X86/X86Instr64bit.td
View File

@ -1251,12 +1251,6 @@ def : Pat<(and GR64:$src, 0xffff),
// r & (2^8-1) ==> movz
def : Pat<(and GR64:$src, 0xff),
(MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
// TODO: The following two patterns could be adapted to apply to x86-32, except
// that they'll need some way to deal with the fact that in x86-32 not all GPRs
// have 8-bit subregs. The GR32_ and GR16_ classes are a step in this direction,
// but they aren't ready for this purpose yet.
// r & (2^8-1) ==> movz
def : Pat<(and GR32:$src1, 0xff),
(MOVZX32rr8 (i8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit)))>,

10
lib/Target/X86/X86InstrInfo.td
View File

@ -2774,6 +2774,16 @@ def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
// r & (2^16-1) ==> movz
def : Pat<(and GR32:$src1, 0xffff),
(MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>;
// r & (2^8-1) ==> movz
def : Pat<(and GR32:$src1, 0xff),
(MOVZX32rr8 (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src1),
x86_subreg_8bit)))>,
Requires<[In32BitMode]>;
// r & (2^8-1) ==> movz
def : Pat<(and GR16:$src1, 0xff),
(MOVZX16rr8 (i8 (EXTRACT_SUBREG (MOV16to16_ GR16:$src1),
x86_subreg_8bit)))>,
Requires<[In32BitMode]>;
// (shl x, 1) ==> (add x, x)
def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;

15
test/CodeGen/X86/zext-inreg-0.ll
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@ -8,11 +8,26 @@
; These should use movzbl instead of 'and 255'.
; This related to not having a ZERO_EXTEND_REG opcode.
define i32 @a(i32 %d) nounwind {
%e = add i32 %d, 1
%retval = and i32 %e, 255
ret i32 %retval
}
define i32 @b(float %d) nounwind {
%tmp12 = fptoui float %d to i8
%retval = zext i8 %tmp12 to i32
ret i32 %retval
}
define i32 @c(i32 %d) nounwind {
%e = add i32 %d, 1
%retval = and i32 %e, 65535
ret i32 %retval
}
define i64 @d(i64 %d) nounwind {
%e = add i64 %d, 1
%retval = and i64 %e, 255
ret i64 %retval
}
define i64 @e(i64 %d) nounwind {
%e = add i64 %d, 1
%retval = and i64 %e, 65535

28
test/CodeGen/X86/zext-inreg-2.ll
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@ -1,28 +0,0 @@
; RUN: llvm-as < %s | llc -march=x86-64 > %t
; RUN: not grep and %t
; RUN: not grep movzbq %t
; RUN: not grep movzwq %t
; RUN: not grep movzlq %t
; These should use movzbl instead of 'and 255'.
; This related to not having a ZERO_EXTEND_REG opcode.
; This test was split out of zext-inreg-0.ll because these
; cases don't yet work on x86-32 due to the 8-bit subreg
; issue.
define i32 @a(i32 %d) nounwind {
%e = add i32 %d, 1
%retval = and i32 %e, 255
ret i32 %retval
}
define i32 @b(float %d) nounwind {
%tmp12 = fptoui float %d to i8
%retval = zext i8 %tmp12 to i32
ret i32 %retval
}
define i64 @d(i64 %d) nounwind {
%e = add i64 %d, 1
%retval = and i64 %e, 255
ret i64 %retval
}