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Fix MBlaze backend call instructions so that arguments passed through registers
are correctly marked as used. This removes a hack where the call instructions marked all possible argument registers as used in the tablegen description. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121994 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -146,7 +146,8 @@ static bool delayHasHazard(MachineBasicBlock::iterator &candidate,
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unsigned aop_reg = a->getOperand(aop).getReg();
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for (unsigned bop = 0, bend = b->getNumOperands(); bop<bend; ++bop) {
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if (b->getOperand(bop).isReg() && (!b->getOperand(bop).isImplicit())) {
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if (b->getOperand(bop).isReg() && !b->getOperand(bop).isImplicit() &&
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!b->getOperand(bop).isKill()) {
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unsigned bop_reg = b->getOperand(bop).getReg();
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if (aop_reg == bop_reg)
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return true;
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@ -19,7 +19,7 @@ include "MBlazeInstrFormats.td"
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// def SDTMBlazeSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>;
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def SDT_MBlazeRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_MBlazeIRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_MBlazeJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def SDT_MBlazeJmpLink : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
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def SDT_MBCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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def SDT_MBCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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@ -33,7 +33,8 @@ def MBlazeIRet : SDNode<"MBlazeISD::IRet", SDT_MBlazeIRet,
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[SDNPHasChain, SDNPOptInFlag]>;
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def MBlazeJmpLink : SDNode<"MBlazeISD::JmpLink",SDT_MBlazeJmpLink,
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[SDNPHasChain,SDNPOptInFlag,SDNPOutFlag]>;
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[SDNPHasChain,SDNPOptInFlag,SDNPOutFlag,
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SDNPVariadic]>;
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def MBWrapper : SDNode<"MBlazeISD::Wrap", SDTIntUnaryOp>;
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@ -290,7 +291,7 @@ class BranchI<bits<6> op, bits<5> br, string instr_asm> :
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// Branch and Link Instructions
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//===----------------------------------------------------------------------===//
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class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
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TA<op, flags, (outs), (ins GPR:$link, GPR:$target),
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TA<op, flags, (outs), (ins GPR:$link, GPR:$target, variable_ops),
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!strconcat(instr_asm, " $link, $target"),
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[], IIBranch> {
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let ra = br;
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@ -298,7 +299,7 @@ class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
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}
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class BranchLI<bits<6> op, bits<5> br, string instr_asm> :
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TB<op, (outs), (ins GPR:$link, calltarget:$target),
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TB<op, (outs), (ins GPR:$link, calltarget:$target, variable_ops),
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!strconcat(instr_asm, " $link, $target"),
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[], IIBranch> {
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let ra = br;
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@ -500,17 +501,16 @@ let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
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def BGED : BranchC<0x27, 0x15, 0x000, "bged ">;
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}
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let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1,
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let isCall =1, hasDelaySlot = 1,
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Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
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Uses = [R1,R5,R6,R7,R8,R9,R10] in {
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Uses = [R1] in {
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def BRLID : BranchLI<0x2E, 0x14, "brlid ">;
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def BRALID : BranchLI<0x2E, 0x1C, "bralid ">;
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}
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let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isIndirectBranch = 1,
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isBarrier = 1,
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let isCall = 1, hasDelaySlot = 1,
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Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
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Uses = [R1,R5,R6,R7,R8,R9,R10] in {
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Uses = [R1] in {
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def BRLD : BranchL<0x26, 0x14, 0x000, "brld ">;
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def BRALD : BranchL<0x26, 0x1C, 0x000, "brald ">;
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}
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