mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
move more pseudo instructions out to X86InstrCompiler.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115598 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
d071b83b5d
commit
8af88ef157
@ -100,23 +100,6 @@ def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
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// Instruction list...
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//
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// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber EFLAGS.
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let Defs = [RSP, EFLAGS], Uses = [RSP] in {
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def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(X86callseq_start timm:$amt)]>,
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Requires<[In64BitMode]>;
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def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP",
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[(X86callseq_end timm:$amt1, timm:$amt2)]>,
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Requires<[In64BitMode]>;
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}
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions...
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@ -1435,40 +1418,6 @@ let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
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"", [(set GR64:$dst, i64immZExt32:$src)]>;
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//===----------------------------------------------------------------------===//
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// Thread Local Storage Instructions
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//===----------------------------------------------------------------------===//
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// ELF TLS Support
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// All calls clobber the non-callee saved registers. RSP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead.
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let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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Uses = [RSP] in
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def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
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".byte\t0x66; "
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"leaq\t$sym(%rip), %rdi; "
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".word\t0x6666; "
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"rex64; "
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"call\t__tls_get_addr@PLT",
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[(X86tlsaddr tls64addr:$sym)]>,
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Requires<[In64BitMode]>;
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// Darwin TLS Support
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// For x86_64, the address of the thunk is passed in %rdi, on return
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// the address of the variable is in %rax. All other registers are preserved.
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let Defs = [RAX],
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Uses = [RDI],
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usesCustomInserter = 1 in
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def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
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"# TLSCall_64",
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[(X86TLSCall addr:$sym)]>,
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Requires<[In64BitMode]>;
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//===----------------------------------------------------------------------===//
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// Atomic Instructions
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//===----------------------------------------------------------------------===//
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@ -12,6 +12,75 @@
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//
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//===----------------------------------------------------------------------===//
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// PIC base construction. This expands to code that looks like this:
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// call $next_inst
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// popl %destreg"
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let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
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def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
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"", []>;
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// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber EFLAGS.
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let Defs = [ESP, EFLAGS], Uses = [ESP] in {
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def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(X86callseq_start timm:$amt)]>,
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Requires<[In32BitMode]>;
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def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP",
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[(X86callseq_end timm:$amt1, timm:$amt2)]>,
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Requires<[In32BitMode]>;
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}
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// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber EFLAGS.
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let Defs = [RSP, EFLAGS], Uses = [RSP] in {
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def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(X86callseq_start timm:$amt)]>,
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Requires<[In64BitMode]>;
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def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP",
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[(X86callseq_end timm:$amt1, timm:$amt2)]>,
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Requires<[In64BitMode]>;
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}
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// x86-64 va_start lowering magic.
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let usesCustomInserter = 1 in {
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def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
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(outs),
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(ins GR8:$al,
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i64imm:$regsavefi, i64imm:$offset,
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variable_ops),
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"#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
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[(X86vastart_save_xmm_regs GR8:$al,
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imm:$regsavefi,
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imm:$offset)]>;
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// Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
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// to _alloca is needed to probe the stack when allocating more than 4k bytes in
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// one go. Touching the stack at 4K increments is necessary to ensure that the
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// guard pages used by the OS virtual memory manager are allocated in correct
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// sequence.
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// The main point of having separate instruction are extra unmodelled effects
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// (compared to ordinary calls) like stack pointer change.
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let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
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def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
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"# dynamic stack allocation",
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[(X86MingwAlloca)]>;
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}
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//===----------------------------------------------------------------------===//
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// EH Pseudo Instructions
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@ -32,6 +101,90 @@ def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
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}
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//===----------------------------------------------------------------------===//
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// Alias Instructions
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//===----------------------------------------------------------------------===//
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// Alias instructions that map movr0 to xor.
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// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
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// FIXME: Set encoding to pseudo.
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let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
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isCodeGenOnly = 1 in {
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def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
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[(set GR8:$dst, 0)]>;
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// We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
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// encoding and avoids a partial-register update sometimes, but doing so
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// at isel time interferes with rematerialization in the current register
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// allocator. For now, this is rewritten when the instruction is lowered
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// to an MCInst.
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def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
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"",
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[(set GR16:$dst, 0)]>, OpSize;
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// FIXME: Set encoding to pseudo.
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def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
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[(set GR32:$dst, 0)]>;
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}
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//===----------------------------------------------------------------------===//
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// Thread Local Storage Instructions
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//
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// ELF TLS Support
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// All calls clobber the non-callee saved registers. ESP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead.
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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Uses = [ESP] in
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def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
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"leal\t$sym, %eax; "
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"call\t___tls_get_addr@PLT",
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[(X86tlsaddr tls32addr:$sym)]>,
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Requires<[In32BitMode]>;
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// All calls clobber the non-callee saved registers. RSP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead.
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let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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Uses = [RSP] in
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def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
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".byte\t0x66; "
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"leaq\t$sym(%rip), %rdi; "
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".word\t0x6666; "
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"rex64; "
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"call\t__tls_get_addr@PLT",
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[(X86tlsaddr tls64addr:$sym)]>,
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Requires<[In64BitMode]>;
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// Darwin TLS Support
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// For i386, the address of the thunk is passed on the stack, on return the
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// address of the variable is in %eax. %ecx is trashed during the function
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// call. All other registers are preserved.
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let Defs = [EAX, ECX],
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Uses = [ESP],
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usesCustomInserter = 1 in
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def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
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"# TLSCall_32",
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[(X86TLSCall addr:$sym)]>,
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Requires<[In32BitMode]>;
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// For x86_64, the address of the thunk is passed in %rdi, on return
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// the address of the variable is in %rax. All other registers are preserved.
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let Defs = [RAX],
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Uses = [RDI],
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usesCustomInserter = 1 in
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def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
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"# TLSCall_64",
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[(X86TLSCall addr:$sym)]>,
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Requires<[In64BitMode]>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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@ -504,48 +504,6 @@ def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
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// Instruction list.
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//
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// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber EFLAGS.
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let Defs = [ESP, EFLAGS], Uses = [ESP] in {
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def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(X86callseq_start timm:$amt)]>,
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Requires<[In32BitMode]>;
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def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP",
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[(X86callseq_end timm:$amt1, timm:$amt2)]>,
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Requires<[In32BitMode]>;
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}
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// x86-64 va_start lowering magic.
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let usesCustomInserter = 1 in {
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def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
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(outs),
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(ins GR8:$al,
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i64imm:$regsavefi, i64imm:$offset,
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variable_ops),
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"#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
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[(X86vastart_save_xmm_regs GR8:$al,
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imm:$regsavefi,
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imm:$offset)]>;
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// Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
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// to _alloca is needed to probe the stack when allocating more than 4k bytes in
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// one go. Touching the stack at 4K increments is necessary to ensure that the
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// guard pages used by the OS virtual memory manager are allocated in correct
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// sequence.
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// The main point of having separate instruction are extra unmodelled effects
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// (compared to ordinary calls) like stack pointer change.
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let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
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def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
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"# dynamic stack allocation",
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[(X86MingwAlloca)]>;
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}
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// Nop
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let neverHasSideEffects = 1 in {
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def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
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@ -555,13 +513,6 @@ let neverHasSideEffects = 1 in {
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"nop{l}\t$zero", []>, TB;
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}
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// PIC base construction. This expands to code that looks like this:
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// call $next_inst
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// popl %destreg"
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let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
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def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
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"", []>;
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// Constructing a stack frame.
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def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
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@ -3538,63 +3489,7 @@ let neverHasSideEffects = 1 in {
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"{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
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}
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//===----------------------------------------------------------------------===//
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// Alias Instructions
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//===----------------------------------------------------------------------===//
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// Alias instructions that map movr0 to xor.
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// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
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// FIXME: Set encoding to pseudo.
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let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
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isCodeGenOnly = 1 in {
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def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
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[(set GR8:$dst, 0)]>;
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// We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
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// encoding and avoids a partial-register update sometimes, but doing so
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// at isel time interferes with rematerialization in the current register
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// allocator. For now, this is rewritten when the instruction is lowered
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// to an MCInst.
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def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
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"",
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[(set GR16:$dst, 0)]>, OpSize;
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// FIXME: Set encoding to pseudo.
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def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
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[(set GR32:$dst, 0)]>;
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}
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//===----------------------------------------------------------------------===//
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// Thread Local Storage Instructions
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//
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// ELF TLS Support
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// All calls clobber the non-callee saved registers. ESP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead.
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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Uses = [ESP] in
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def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
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"leal\t$sym, %eax; "
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"call\t___tls_get_addr@PLT",
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[(X86tlsaddr tls32addr:$sym)]>,
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Requires<[In32BitMode]>;
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// Darwin TLS Support
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// For i386, the address of the thunk is passed on the stack, on return the
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// address of the variable is in %eax. %ecx is trashed during the function
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// call. All other registers are preserved.
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let Defs = [EAX, ECX],
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Uses = [ESP],
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usesCustomInserter = 1 in
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def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
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"# TLSCall_32",
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[(X86TLSCall addr:$sym)]>,
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Requires<[In32BitMode]>;
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//===----------------------------------------------------------------------===//
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// Atomic support
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