mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115598 91177308-0d34-0410-b5e6-96231b3b80d8
1114 lines
49 KiB
TableGen
1114 lines
49 KiB
TableGen
//===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the various pseudo instructions used by the compiler,
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// as well as Pat patterns used during instruction selection.
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//
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//===----------------------------------------------------------------------===//
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// PIC base construction. This expands to code that looks like this:
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// call $next_inst
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// popl %destreg"
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let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
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def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
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"", []>;
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// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber EFLAGS.
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let Defs = [ESP, EFLAGS], Uses = [ESP] in {
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def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(X86callseq_start timm:$amt)]>,
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Requires<[In32BitMode]>;
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def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP",
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[(X86callseq_end timm:$amt1, timm:$amt2)]>,
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Requires<[In32BitMode]>;
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}
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// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber EFLAGS.
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let Defs = [RSP, EFLAGS], Uses = [RSP] in {
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def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(X86callseq_start timm:$amt)]>,
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Requires<[In64BitMode]>;
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def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP",
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[(X86callseq_end timm:$amt1, timm:$amt2)]>,
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Requires<[In64BitMode]>;
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}
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// x86-64 va_start lowering magic.
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let usesCustomInserter = 1 in {
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def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
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(outs),
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(ins GR8:$al,
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i64imm:$regsavefi, i64imm:$offset,
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variable_ops),
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"#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
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[(X86vastart_save_xmm_regs GR8:$al,
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imm:$regsavefi,
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imm:$offset)]>;
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// Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
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// to _alloca is needed to probe the stack when allocating more than 4k bytes in
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// one go. Touching the stack at 4K increments is necessary to ensure that the
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// guard pages used by the OS virtual memory manager are allocated in correct
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// sequence.
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// The main point of having separate instruction are extra unmodelled effects
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// (compared to ordinary calls) like stack pointer change.
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let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
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def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
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"# dynamic stack allocation",
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[(X86MingwAlloca)]>;
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}
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//===----------------------------------------------------------------------===//
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// EH Pseudo Instructions
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//
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let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1, isCodeGenOnly = 1 in {
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def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
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"ret\t#eh_return, addr: $addr",
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[(X86ehret GR32:$addr)]>;
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}
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let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1, isCodeGenOnly = 1 in {
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def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
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"ret\t#eh_return, addr: $addr",
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[(X86ehret GR64:$addr)]>;
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}
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//===----------------------------------------------------------------------===//
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// Alias Instructions
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//===----------------------------------------------------------------------===//
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// Alias instructions that map movr0 to xor.
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// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
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// FIXME: Set encoding to pseudo.
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let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
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isCodeGenOnly = 1 in {
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def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
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[(set GR8:$dst, 0)]>;
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// We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
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// encoding and avoids a partial-register update sometimes, but doing so
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// at isel time interferes with rematerialization in the current register
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// allocator. For now, this is rewritten when the instruction is lowered
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// to an MCInst.
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def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
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"",
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[(set GR16:$dst, 0)]>, OpSize;
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// FIXME: Set encoding to pseudo.
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def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
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[(set GR32:$dst, 0)]>;
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}
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//===----------------------------------------------------------------------===//
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// Thread Local Storage Instructions
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//
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// ELF TLS Support
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// All calls clobber the non-callee saved registers. ESP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead.
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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Uses = [ESP] in
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def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
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"leal\t$sym, %eax; "
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"call\t___tls_get_addr@PLT",
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[(X86tlsaddr tls32addr:$sym)]>,
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Requires<[In32BitMode]>;
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// All calls clobber the non-callee saved registers. RSP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead.
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let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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Uses = [RSP] in
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def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
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".byte\t0x66; "
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"leaq\t$sym(%rip), %rdi; "
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".word\t0x6666; "
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"rex64; "
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"call\t__tls_get_addr@PLT",
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[(X86tlsaddr tls64addr:$sym)]>,
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Requires<[In64BitMode]>;
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// Darwin TLS Support
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// For i386, the address of the thunk is passed on the stack, on return the
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// address of the variable is in %eax. %ecx is trashed during the function
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// call. All other registers are preserved.
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let Defs = [EAX, ECX],
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Uses = [ESP],
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usesCustomInserter = 1 in
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def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
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"# TLSCall_32",
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[(X86TLSCall addr:$sym)]>,
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Requires<[In32BitMode]>;
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// For x86_64, the address of the thunk is passed in %rdi, on return
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// the address of the variable is in %rax. All other registers are preserved.
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let Defs = [RAX],
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Uses = [RDI],
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usesCustomInserter = 1 in
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def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
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"# TLSCall_64",
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[(X86TLSCall addr:$sym)]>,
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Requires<[In64BitMode]>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
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def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
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def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
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def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
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def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
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def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
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def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
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def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
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(ADD32ri GR32:$src1, tconstpool:$src2)>;
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def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
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(ADD32ri GR32:$src1, tjumptable:$src2)>;
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def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
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(ADD32ri GR32:$src1, tglobaladdr:$src2)>;
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def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
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(ADD32ri GR32:$src1, texternalsym:$src2)>;
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def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
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(ADD32ri GR32:$src1, tblockaddress:$src2)>;
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def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
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(MOV32mi addr:$dst, tglobaladdr:$src)>;
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def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
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(MOV32mi addr:$dst, texternalsym:$src)>;
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def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
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(MOV32mi addr:$dst, tblockaddress:$src)>;
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// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
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// code model mode, should use 'movabs'. FIXME: This is really a hack, the
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// 'movabs' predicate should handle this sort of thing.
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def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
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(MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
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def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
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(MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
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def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
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(MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
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def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
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(MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
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def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
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(MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
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// In static codegen with small code model, we can get the address of a label
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// into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
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// the MOV64ri64i32 should accept these.
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def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
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(MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
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def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
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(MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
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def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
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(MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
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def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
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(MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
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def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
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(MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
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// In kernel code model, we can get the address of a label
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// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
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// the MOV64ri32 should accept these.
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def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
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(MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
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def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
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(MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
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def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
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(MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
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def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
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(MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
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def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
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(MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
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// If we have small model and -static mode, it is safe to store global addresses
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// directly as immediates. FIXME: This is really a hack, the 'imm' predicate
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// for MOV64mi32 should handle this sort of thing.
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def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tconstpool:$src)>,
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Requires<[NearData, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tjumptable:$src)>,
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Requires<[NearData, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tglobaladdr:$src)>,
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Requires<[NearData, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, texternalsym:$src)>,
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Requires<[NearData, IsStatic]>;
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def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
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(MOV64mi32 addr:$dst, tblockaddress:$src)>,
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Requires<[NearData, IsStatic]>;
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// Calls
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// tls has some funny stuff here...
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// This corresponds to movabs $foo@tpoff, %rax
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def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
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(MOV64ri tglobaltlsaddr :$dst)>;
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// This corresponds to add $foo@tpoff, %rax
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def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
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(ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
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// This corresponds to mov foo@tpoff(%rbx), %eax
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def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
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(MOV64rm tglobaltlsaddr :$dst)>;
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// Direct PC relative function call for small code model. 32-bit displacement
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// sign extended to 64-bit.
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def : Pat<(X86call (i64 tglobaladdr:$dst)),
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(CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
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def : Pat<(X86call (i64 texternalsym:$dst)),
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(CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
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def : Pat<(X86call (i64 tglobaladdr:$dst)),
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(WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
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def : Pat<(X86call (i64 texternalsym:$dst)),
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(WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
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// tailcall stuff
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def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
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(TCRETURNri GR32_TC:$dst, imm:$off)>,
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Requires<[In32BitMode]>;
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// FIXME: This is disabled for 32-bit PIC mode because the global base
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// register which is part of the address mode may be assigned a
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// callee-saved register.
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def : Pat<(X86tcret (load addr:$dst), imm:$off),
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(TCRETURNmi addr:$dst, imm:$off)>,
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Requires<[In32BitMode, IsNotPIC]>;
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def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
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(TCRETURNdi texternalsym:$dst, imm:$off)>,
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Requires<[In32BitMode]>;
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def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
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(TCRETURNdi texternalsym:$dst, imm:$off)>,
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Requires<[In32BitMode]>;
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def : Pat<(X86tcret GR64_TC:$dst, imm:$off),
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(TCRETURNri64 GR64_TC:$dst, imm:$off)>,
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Requires<[In64BitMode]>;
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def : Pat<(X86tcret (load addr:$dst), imm:$off),
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(TCRETURNmi64 addr:$dst, imm:$off)>,
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Requires<[In64BitMode]>;
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def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
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(TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
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Requires<[In64BitMode]>;
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def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
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(TCRETURNdi64 texternalsym:$dst, imm:$off)>,
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Requires<[In64BitMode]>;
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// Normal calls, with various flavors of addresses.
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def : Pat<(X86call (i32 tglobaladdr:$dst)),
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(CALLpcrel32 tglobaladdr:$dst)>;
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def : Pat<(X86call (i32 texternalsym:$dst)),
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(CALLpcrel32 texternalsym:$dst)>;
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def : Pat<(X86call (i32 imm:$dst)),
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(CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
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// X86 specific add which produces a flag.
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def : Pat<(addc GR32:$src1, GR32:$src2),
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(ADD32rr GR32:$src1, GR32:$src2)>;
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def : Pat<(addc GR32:$src1, (load addr:$src2)),
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(ADD32rm GR32:$src1, addr:$src2)>;
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def : Pat<(addc GR32:$src1, imm:$src2),
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(ADD32ri GR32:$src1, imm:$src2)>;
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def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
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(ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
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def : Pat<(addc GR64:$src1, GR64:$src2),
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(ADD64rr GR64:$src1, GR64:$src2)>;
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def : Pat<(addc GR64:$src1, (load addr:$src2)),
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(ADD64rm GR64:$src1, addr:$src2)>;
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def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
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(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
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def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
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(ADD64ri32 GR64:$src1, imm:$src2)>;
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def : Pat<(subc GR32:$src1, GR32:$src2),
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(SUB32rr GR32:$src1, GR32:$src2)>;
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def : Pat<(subc GR32:$src1, (load addr:$src2)),
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(SUB32rm GR32:$src1, addr:$src2)>;
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def : Pat<(subc GR32:$src1, imm:$src2),
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(SUB32ri GR32:$src1, imm:$src2)>;
|
|
def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
|
|
(SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|
|
|
def : Pat<(subc GR64:$src1, GR64:$src2),
|
|
(SUB64rr GR64:$src1, GR64:$src2)>;
|
|
def : Pat<(subc GR64:$src1, (load addr:$src2)),
|
|
(SUB64rm GR64:$src1, addr:$src2)>;
|
|
def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
|
|
(SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(subc GR64:$src1, imm:$src2),
|
|
(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
|
|
// Comparisons.
|
|
|
|
// TEST R,R is smaller than CMP R,0
|
|
def : Pat<(X86cmp GR8:$src1, 0),
|
|
(TEST8rr GR8:$src1, GR8:$src1)>;
|
|
def : Pat<(X86cmp GR16:$src1, 0),
|
|
(TEST16rr GR16:$src1, GR16:$src1)>;
|
|
def : Pat<(X86cmp GR32:$src1, 0),
|
|
(TEST32rr GR32:$src1, GR32:$src1)>;
|
|
def : Pat<(X86cmp GR64:$src1, 0),
|
|
(TEST64rr GR64:$src1, GR64:$src1)>;
|
|
|
|
// Conditional moves with folded loads with operands swapped and conditions
|
|
// inverted.
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
|
|
(CMOVAE16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
|
|
(CMOVAE32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
|
|
(CMOVB16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
|
|
(CMOVB32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
|
|
(CMOVNE16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
|
|
(CMOVNE32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
|
|
(CMOVE16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
|
|
(CMOVE32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
|
|
(CMOVA16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
|
|
(CMOVA32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
|
|
(CMOVBE16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
|
|
(CMOVBE32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
|
|
(CMOVGE16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
|
|
(CMOVGE32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
|
|
(CMOVL16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
|
|
(CMOVL32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
|
|
(CMOVG16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
|
|
(CMOVG32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
|
|
(CMOVLE16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
|
|
(CMOVLE32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
|
|
(CMOVNP16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
|
|
(CMOVNP32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
|
|
(CMOVP16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
|
|
(CMOVP32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
|
|
(CMOVNS16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
|
|
(CMOVNS32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
|
|
(CMOVS16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
|
|
(CMOVS32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
|
|
(CMOVNO16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
|
|
(CMOVNO32rm GR32:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
|
|
(CMOVO16rm GR16:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
|
|
(CMOVO32rm GR32:$src2, addr:$src1)>;
|
|
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
|
|
(CMOVAE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
|
|
(CMOVB64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
|
|
(CMOVNE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
|
|
(CMOVE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
|
|
(CMOVA64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
|
|
(CMOVBE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
|
|
(CMOVGE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
|
|
(CMOVL64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
|
|
(CMOVG64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
|
|
(CMOVLE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
|
|
(CMOVNP64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
|
|
(CMOVP64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
|
|
(CMOVNS64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
|
|
(CMOVS64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
|
|
(CMOVNO64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
|
|
(CMOVO64rm GR64:$src2, addr:$src1)>;
|
|
|
|
|
|
// zextload bool -> zextload byte
|
|
def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
|
|
def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
|
|
def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
|
|
def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
|
|
|
|
// extload bool -> extload byte
|
|
// When extloading from 16-bit and smaller memory locations into 64-bit
|
|
// registers, use zero-extending loads so that the entire 64-bit register is
|
|
// defined, avoiding partial-register updates.
|
|
|
|
def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
|
|
def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
|
|
def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
|
|
def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
|
|
def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
|
|
def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
|
|
|
|
def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
|
|
def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
|
|
def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
|
|
// For other extloads, use subregs, since the high contents of the register are
|
|
// defined after an extload.
|
|
def : Pat<(extloadi64i32 addr:$src),
|
|
(SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
|
|
sub_32bit)>;
|
|
|
|
// anyext. Define these to do an explicit zero-extend to
|
|
// avoid partial-register updates.
|
|
def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
|
|
def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
|
|
|
|
// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
|
|
def : Pat<(i32 (anyext GR16:$src)),
|
|
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
|
|
|
|
def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
|
|
def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
|
|
def : Pat<(i64 (anyext GR32:$src)),
|
|
(SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Some peepholes
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Odd encoding trick: -128 fits into an 8-bit immediate field while
|
|
// +128 doesn't, so in this special case use a sub instead of an add.
|
|
def : Pat<(add GR16:$src1, 128),
|
|
(SUB16ri8 GR16:$src1, -128)>;
|
|
def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
|
|
(SUB16mi8 addr:$dst, -128)>;
|
|
|
|
def : Pat<(add GR32:$src1, 128),
|
|
(SUB32ri8 GR32:$src1, -128)>;
|
|
def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
|
|
(SUB32mi8 addr:$dst, -128)>;
|
|
|
|
def : Pat<(add GR64:$src1, 128),
|
|
(SUB64ri8 GR64:$src1, -128)>;
|
|
def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
|
|
(SUB64mi8 addr:$dst, -128)>;
|
|
|
|
// The same trick applies for 32-bit immediate fields in 64-bit
|
|
// instructions.
|
|
def : Pat<(add GR64:$src1, 0x0000000080000000),
|
|
(SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
|
|
def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
|
|
(SUB64mi32 addr:$dst, 0xffffffff80000000)>;
|
|
|
|
// Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
|
|
// has an immediate with at least 32 bits of leading zeros, to avoid needing to
|
|
// materialize that immediate in a register first.
|
|
def : Pat<(and GR64:$src, i64immZExt32:$imm),
|
|
(SUBREG_TO_REG
|
|
(i64 0),
|
|
(AND32ri
|
|
(EXTRACT_SUBREG GR64:$src, sub_32bit),
|
|
(i32 (GetLo32XForm imm:$imm))),
|
|
sub_32bit)>;
|
|
|
|
|
|
// r & (2^16-1) ==> movz
|
|
def : Pat<(and GR32:$src1, 0xffff),
|
|
(MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
|
|
// r & (2^8-1) ==> movz
|
|
def : Pat<(and GR32:$src1, 0xff),
|
|
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
|
|
GR32_ABCD)),
|
|
sub_8bit))>,
|
|
Requires<[In32BitMode]>;
|
|
// r & (2^8-1) ==> movz
|
|
def : Pat<(and GR16:$src1, 0xff),
|
|
(MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
|
|
GR16_ABCD)),
|
|
sub_8bit))>,
|
|
Requires<[In32BitMode]>;
|
|
|
|
// r & (2^32-1) ==> movz
|
|
def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
|
|
(MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
|
|
// r & (2^16-1) ==> movz
|
|
def : Pat<(and GR64:$src, 0xffff),
|
|
(MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
|
|
// r & (2^8-1) ==> movz
|
|
def : Pat<(and GR64:$src, 0xff),
|
|
(MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
|
|
// r & (2^8-1) ==> movz
|
|
def : Pat<(and GR32:$src1, 0xff),
|
|
(MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
|
|
Requires<[In64BitMode]>;
|
|
// r & (2^8-1) ==> movz
|
|
def : Pat<(and GR16:$src1, 0xff),
|
|
(MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
|
|
// sext_inreg patterns
|
|
def : Pat<(sext_inreg GR32:$src, i16),
|
|
(MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
|
|
def : Pat<(sext_inreg GR32:$src, i8),
|
|
(MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
|
GR32_ABCD)),
|
|
sub_8bit))>,
|
|
Requires<[In32BitMode]>;
|
|
def : Pat<(sext_inreg GR16:$src, i8),
|
|
(MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
|
GR16_ABCD)),
|
|
sub_8bit))>,
|
|
Requires<[In32BitMode]>;
|
|
|
|
def : Pat<(sext_inreg GR64:$src, i32),
|
|
(MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
|
|
def : Pat<(sext_inreg GR64:$src, i16),
|
|
(MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
|
|
def : Pat<(sext_inreg GR64:$src, i8),
|
|
(MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
|
|
def : Pat<(sext_inreg GR32:$src, i8),
|
|
(MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(sext_inreg GR16:$src, i8),
|
|
(MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
|
|
// trunc patterns
|
|
def : Pat<(i16 (trunc GR32:$src)),
|
|
(EXTRACT_SUBREG GR32:$src, sub_16bit)>;
|
|
def : Pat<(i8 (trunc GR32:$src)),
|
|
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
|
|
sub_8bit)>,
|
|
Requires<[In32BitMode]>;
|
|
def : Pat<(i8 (trunc GR16:$src)),
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
sub_8bit)>,
|
|
Requires<[In32BitMode]>;
|
|
def : Pat<(i32 (trunc GR64:$src)),
|
|
(EXTRACT_SUBREG GR64:$src, sub_32bit)>;
|
|
def : Pat<(i16 (trunc GR64:$src)),
|
|
(EXTRACT_SUBREG GR64:$src, sub_16bit)>;
|
|
def : Pat<(i8 (trunc GR64:$src)),
|
|
(EXTRACT_SUBREG GR64:$src, sub_8bit)>;
|
|
def : Pat<(i8 (trunc GR32:$src)),
|
|
(EXTRACT_SUBREG GR32:$src, sub_8bit)>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(i8 (trunc GR16:$src)),
|
|
(EXTRACT_SUBREG GR16:$src, sub_8bit)>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
// h-register tricks
|
|
def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
sub_8bit_hi)>,
|
|
Requires<[In32BitMode]>;
|
|
def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
|
|
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
|
|
sub_8bit_hi)>,
|
|
Requires<[In32BitMode]>;
|
|
def : Pat<(srl GR16:$src, (i8 8)),
|
|
(EXTRACT_SUBREG
|
|
(MOVZX32rr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
sub_8bit_hi)),
|
|
sub_16bit)>,
|
|
Requires<[In32BitMode]>;
|
|
def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
|
|
(MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
|
GR16_ABCD)),
|
|
sub_8bit_hi))>,
|
|
Requires<[In32BitMode]>;
|
|
def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
|
|
(MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
|
GR16_ABCD)),
|
|
sub_8bit_hi))>,
|
|
Requires<[In32BitMode]>;
|
|
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
|
|
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
|
GR32_ABCD)),
|
|
sub_8bit_hi))>,
|
|
Requires<[In32BitMode]>;
|
|
def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
|
|
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
|
GR32_ABCD)),
|
|
sub_8bit_hi))>,
|
|
Requires<[In32BitMode]>;
|
|
|
|
// h-register tricks.
|
|
// For now, be conservative on x86-64 and use an h-register extract only if the
|
|
// value is immediately zero-extended or stored, which are somewhat common
|
|
// cases. This uses a bunch of code to prevent a register requiring a REX prefix
|
|
// from being allocated in the same instruction as the h register, as there's
|
|
// currently no way to describe this requirement to the register allocator.
|
|
|
|
// h-register extract and zero-extend.
|
|
def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
|
|
(SUBREG_TO_REG
|
|
(i64 0),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
|
|
sub_8bit_hi)),
|
|
sub_32bit)>;
|
|
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
|
|
sub_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
|
|
(MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
|
GR32_ABCD)),
|
|
sub_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(srl GR16:$src, (i8 8)),
|
|
(EXTRACT_SUBREG
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
sub_8bit_hi)),
|
|
sub_16bit)>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
sub_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
sub_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
|
|
(SUBREG_TO_REG
|
|
(i64 0),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
sub_8bit_hi)),
|
|
sub_32bit)>;
|
|
def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
|
|
(SUBREG_TO_REG
|
|
(i64 0),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
sub_8bit_hi)),
|
|
sub_32bit)>;
|
|
|
|
// h-register extract and store.
|
|
def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
|
|
(MOV8mr_NOREX
|
|
addr:$dst,
|
|
(EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
|
|
sub_8bit_hi))>;
|
|
def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
|
|
(MOV8mr_NOREX
|
|
addr:$dst,
|
|
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
|
|
sub_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
|
|
(MOV8mr_NOREX
|
|
addr:$dst,
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
sub_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
|
|
// (shl x, 1) ==> (add x, x)
|
|
def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
|
|
def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
|
|
def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
|
|
def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
|
|
|
|
// (shl x (and y, 31)) ==> (shl x, y)
|
|
def : Pat<(shl GR8:$src1, (and CL, 31)),
|
|
(SHL8rCL GR8:$src1)>;
|
|
def : Pat<(shl GR16:$src1, (and CL, 31)),
|
|
(SHL16rCL GR16:$src1)>;
|
|
def : Pat<(shl GR32:$src1, (and CL, 31)),
|
|
(SHL32rCL GR32:$src1)>;
|
|
def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
|
|
(SHL8mCL addr:$dst)>;
|
|
def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
|
|
(SHL16mCL addr:$dst)>;
|
|
def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
|
|
(SHL32mCL addr:$dst)>;
|
|
|
|
def : Pat<(srl GR8:$src1, (and CL, 31)),
|
|
(SHR8rCL GR8:$src1)>;
|
|
def : Pat<(srl GR16:$src1, (and CL, 31)),
|
|
(SHR16rCL GR16:$src1)>;
|
|
def : Pat<(srl GR32:$src1, (and CL, 31)),
|
|
(SHR32rCL GR32:$src1)>;
|
|
def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
|
|
(SHR8mCL addr:$dst)>;
|
|
def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
|
|
(SHR16mCL addr:$dst)>;
|
|
def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
|
|
(SHR32mCL addr:$dst)>;
|
|
|
|
def : Pat<(sra GR8:$src1, (and CL, 31)),
|
|
(SAR8rCL GR8:$src1)>;
|
|
def : Pat<(sra GR16:$src1, (and CL, 31)),
|
|
(SAR16rCL GR16:$src1)>;
|
|
def : Pat<(sra GR32:$src1, (and CL, 31)),
|
|
(SAR32rCL GR32:$src1)>;
|
|
def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
|
|
(SAR8mCL addr:$dst)>;
|
|
def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
|
|
(SAR16mCL addr:$dst)>;
|
|
def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
|
|
(SAR32mCL addr:$dst)>;
|
|
|
|
// (shl x (and y, 63)) ==> (shl x, y)
|
|
def : Pat<(shl GR64:$src1, (and CL, 63)),
|
|
(SHL64rCL GR64:$src1)>;
|
|
def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
|
|
(SHL64mCL addr:$dst)>;
|
|
|
|
def : Pat<(srl GR64:$src1, (and CL, 63)),
|
|
(SHR64rCL GR64:$src1)>;
|
|
def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
|
|
(SHR64mCL addr:$dst)>;
|
|
|
|
def : Pat<(sra GR64:$src1, (and CL, 63)),
|
|
(SAR64rCL GR64:$src1)>;
|
|
def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
|
|
(SAR64mCL addr:$dst)>;
|
|
|
|
|
|
// (anyext (setcc_carry)) -> (setcc_carry)
|
|
def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
|
|
(SETB_C16r)>;
|
|
def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
|
|
(SETB_C32r)>;
|
|
def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
|
|
(SETB_C32r)>;
|
|
|
|
// (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
|
|
let AddedComplexity = 5 in { // Try this before the selecting to OR
|
|
def : Pat<(or_is_add GR16:$src1, imm:$src2),
|
|
(ADD16ri GR16:$src1, imm:$src2)>;
|
|
def : Pat<(or_is_add GR32:$src1, imm:$src2),
|
|
(ADD32ri GR32:$src1, imm:$src2)>;
|
|
def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
|
|
(ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
|
def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
|
|
(ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|
def : Pat<(or_is_add GR16:$src1, GR16:$src2),
|
|
(ADD16rr GR16:$src1, GR16:$src2)>;
|
|
def : Pat<(or_is_add GR32:$src1, GR32:$src2),
|
|
(ADD32rr GR32:$src1, GR32:$src2)>;
|
|
def : Pat<(or_is_add GR64:$src1, i64immSExt8:$src2),
|
|
(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(or_is_add GR64:$src1, i64immSExt32:$src2),
|
|
(ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
def : Pat<(or_is_add GR64:$src1, GR64:$src2),
|
|
(ADD64rr GR64:$src1, GR64:$src2)>;
|
|
} // AddedComplexity
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// EFLAGS-defining Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// add reg, reg
|
|
def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
|
|
def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
|
|
def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
|
|
|
|
// add reg, mem
|
|
def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
|
|
(ADD8rm GR8:$src1, addr:$src2)>;
|
|
def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
|
|
(ADD16rm GR16:$src1, addr:$src2)>;
|
|
def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
|
|
(ADD32rm GR32:$src1, addr:$src2)>;
|
|
|
|
// add reg, imm
|
|
def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
|
|
def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
|
|
def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
|
|
def : Pat<(add GR16:$src1, i16immSExt8:$src2),
|
|
(ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
|
def : Pat<(add GR32:$src1, i32immSExt8:$src2),
|
|
(ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|
|
|
// sub reg, reg
|
|
def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
|
|
def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
|
|
def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
|
|
|
|
// sub reg, mem
|
|
def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
|
|
(SUB8rm GR8:$src1, addr:$src2)>;
|
|
def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
|
|
(SUB16rm GR16:$src1, addr:$src2)>;
|
|
def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
|
|
(SUB32rm GR32:$src1, addr:$src2)>;
|
|
|
|
// sub reg, imm
|
|
def : Pat<(sub GR8:$src1, imm:$src2),
|
|
(SUB8ri GR8:$src1, imm:$src2)>;
|
|
def : Pat<(sub GR16:$src1, imm:$src2),
|
|
(SUB16ri GR16:$src1, imm:$src2)>;
|
|
def : Pat<(sub GR32:$src1, imm:$src2),
|
|
(SUB32ri GR32:$src1, imm:$src2)>;
|
|
def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
|
|
(SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
|
def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
|
|
(SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|
|
|
// mul reg, reg
|
|
def : Pat<(mul GR16:$src1, GR16:$src2),
|
|
(IMUL16rr GR16:$src1, GR16:$src2)>;
|
|
def : Pat<(mul GR32:$src1, GR32:$src2),
|
|
(IMUL32rr GR32:$src1, GR32:$src2)>;
|
|
|
|
// mul reg, mem
|
|
def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
|
|
(IMUL16rm GR16:$src1, addr:$src2)>;
|
|
def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
|
|
(IMUL32rm GR32:$src1, addr:$src2)>;
|
|
|
|
// mul reg, imm
|
|
def : Pat<(mul GR16:$src1, imm:$src2),
|
|
(IMUL16rri GR16:$src1, imm:$src2)>;
|
|
def : Pat<(mul GR32:$src1, imm:$src2),
|
|
(IMUL32rri GR32:$src1, imm:$src2)>;
|
|
def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
|
|
(IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
|
|
def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
|
|
(IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
|
|
|
|
// reg = mul mem, imm
|
|
def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
|
|
(IMUL16rmi addr:$src1, imm:$src2)>;
|
|
def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
|
|
(IMUL32rmi addr:$src1, imm:$src2)>;
|
|
def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
|
|
(IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
|
|
def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
|
|
(IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
|
|
|
|
// Optimize multiply by 2 with EFLAGS result.
|
|
let AddedComplexity = 2 in {
|
|
def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
|
|
def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
|
|
}
|
|
|
|
// Patterns for nodes that do not produce flags, for instructions that do.
|
|
|
|
// addition
|
|
def : Pat<(add GR64:$src1, GR64:$src2),
|
|
(ADD64rr GR64:$src1, GR64:$src2)>;
|
|
def : Pat<(add GR64:$src1, i64immSExt8:$src2),
|
|
(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(add GR64:$src1, i64immSExt32:$src2),
|
|
(ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
|
|
(ADD64rm GR64:$src1, addr:$src2)>;
|
|
|
|
// subtraction
|
|
def : Pat<(sub GR64:$src1, GR64:$src2),
|
|
(SUB64rr GR64:$src1, GR64:$src2)>;
|
|
def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
|
|
(SUB64rm GR64:$src1, addr:$src2)>;
|
|
def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
|
|
(SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
|
|
(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
|
|
// Multiply
|
|
def : Pat<(mul GR64:$src1, GR64:$src2),
|
|
(IMUL64rr GR64:$src1, GR64:$src2)>;
|
|
def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
|
|
(IMUL64rm GR64:$src1, addr:$src2)>;
|
|
def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
|
|
(IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
|
|
(IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
|
|
(IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
|
|
(IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
|
|
|
|
// Increment reg.
|
|
def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
|
|
def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
|
|
def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
|
|
def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
|
|
def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
|
|
def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
|
|
|
|
// Decrement reg.
|
|
def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
|
|
def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
|
|
def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
|
|
def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
|
|
def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
|
|
def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
|
|
|
|
// or reg/reg.
|
|
def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
|
|
def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
|
|
def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
|
|
def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
|
|
|
|
// or reg/mem
|
|
def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
|
|
(OR8rm GR8:$src1, addr:$src2)>;
|
|
def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
|
|
(OR16rm GR16:$src1, addr:$src2)>;
|
|
def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
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(OR32rm GR32:$src1, addr:$src2)>;
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def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
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(OR64rm GR64:$src1, addr:$src2)>;
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// or reg/imm
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def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
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def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
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def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
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def : Pat<(or GR16:$src1, i16immSExt8:$src2),
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(OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
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def : Pat<(or GR32:$src1, i32immSExt8:$src2),
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(OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
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def : Pat<(or GR64:$src1, i64immSExt8:$src2),
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(OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
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def : Pat<(or GR64:$src1, i64immSExt32:$src2),
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(OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
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// xor reg/reg
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def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
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def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
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def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
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def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
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// xor reg/mem
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def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
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(XOR8rm GR8:$src1, addr:$src2)>;
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def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
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(XOR16rm GR16:$src1, addr:$src2)>;
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def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
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(XOR32rm GR32:$src1, addr:$src2)>;
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def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
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(XOR64rm GR64:$src1, addr:$src2)>;
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// xor reg/imm
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def : Pat<(xor GR8:$src1, imm:$src2),
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(XOR8ri GR8:$src1, imm:$src2)>;
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def : Pat<(xor GR16:$src1, imm:$src2),
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(XOR16ri GR16:$src1, imm:$src2)>;
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def : Pat<(xor GR32:$src1, imm:$src2),
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(XOR32ri GR32:$src1, imm:$src2)>;
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def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
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(XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
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def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
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(XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
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def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
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(XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
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def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
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(XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
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// and reg/reg
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def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
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def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
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def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
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def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
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// and reg/mem
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def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
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(AND8rm GR8:$src1, addr:$src2)>;
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def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
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(AND16rm GR16:$src1, addr:$src2)>;
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def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
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(AND32rm GR32:$src1, addr:$src2)>;
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def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
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(AND64rm GR64:$src1, addr:$src2)>;
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// and reg/imm
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def : Pat<(and GR8:$src1, imm:$src2),
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(AND8ri GR8:$src1, imm:$src2)>;
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def : Pat<(and GR16:$src1, imm:$src2),
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(AND16ri GR16:$src1, imm:$src2)>;
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def : Pat<(and GR32:$src1, imm:$src2),
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(AND32ri GR32:$src1, imm:$src2)>;
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def : Pat<(and GR16:$src1, i16immSExt8:$src2),
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(AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
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def : Pat<(and GR32:$src1, i32immSExt8:$src2),
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(AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
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def : Pat<(and GR64:$src1, i64immSExt8:$src2),
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(AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
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def : Pat<(and GR64:$src1, i64immSExt32:$src2),
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(AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
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