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Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in LowerSubregs and add more debugging output there.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41005 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christopher Lamb 2007-08-10 21:11:55 +00:00
parent 6b4af744b8
commit 8b165731bc
2 changed files with 35 additions and 17 deletions
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11
include/llvm/Target/MRegisterInfo.h
View File

@ -360,6 +360,17 @@ public:
return get(RegNo).SuperRegs;
}
/// isSubRegOf - Predicate which returns true if RegA is a sub-register of
/// RegB. Returns false otherwise.
///
bool isSubRegOf(unsigned RegA, unsigned RegB) const {
const TargetRegisterDesc &RD = (*this)[RegA];
for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
if (*reg == RegB)
return true;
return false;
}
/// getName - Return the symbolic target specific name for the specified
/// physical register.
const char *getName(unsigned RegNo) const {

41
lib/CodeGen/LowerSubregs.cpp
View File

@ -59,17 +59,6 @@ static const TargetRegisterClass *getPhysicalRegisterRegClass(
return 0;
}
static bool isSubRegOf(const MRegisterInfo &MRI,
unsigned SubReg,
unsigned SupReg) {
const TargetRegisterDesc &RD = MRI[SubReg];
for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
if (*reg == SupReg)
return true;
return false;
}
bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
@ -105,7 +94,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
}
DOUT << "\n";
MBB->erase(MI);
MBB->remove(MI);
return true;
}
@ -157,8 +146,8 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
// of the destination, we copy the subreg into the source
// However, this is only safe if the insert instruction is the kill
// of the source register
bool revCopyOrder = isSubRegOf(MRI, InsReg, DstReg);
if (revCopyOrder) {
bool revCopyOrder = MRI.isSubRegOf(InsReg, DstReg);
if (revCopyOrder && InsReg != DstSubReg) {
if (MI->getOperand(1).isKill()) {
DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
// Insert sub-register copy
@ -168,14 +157,21 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
} else {
TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
}
MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI);
#endif
} else {
assert(0 && "Don't know how to convert this insert");
}
}
#ifndef NDEBUG
if (InsReg == DstSubReg) {
DOUT << "subreg: Eliminated subreg copy\n";
}
#endif
if (SrcReg != DstReg) {
// Insert super-register copy
@ -189,9 +185,18 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
"Insert superreg and Dst must be of same register class");
MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI);
#endif
}
#ifndef NDEBUG
if (SrcReg == DstReg) {
DOUT << "subreg: Eliminated superreg copy\n";
}
#endif
if (!revCopyOrder && InsReg != DstSubReg) {
// Insert sub-register copy
@ -201,14 +206,16 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
} else {
TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
}
MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI);
#endif
}
DOUT << "\n";
MBB->erase(MI);
MBB->remove(MI);
return true;
}