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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
revert r117858 while I check out a failure I missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1166,7 +1166,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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// FIXME: remove when we have a way to marking a MI with these properties.
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// FIXME: Should pc be an implicit operand like PICADD, etc?
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
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hasExtraDefRegAllocReq = 1 in
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def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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reglist:$dsts, variable_ops),
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IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
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@ -1416,7 +1416,6 @@ def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
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}
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// Store Return State is a system instruction -- for disassembly only
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let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
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def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode),
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NoItinerary, "srs${addr:submode}\tsp!, $mode",
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[/* For disassembly only; pattern left blank */]> {
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@ -1445,7 +1444,6 @@ def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base),
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let Inst{31-28} = 0b1111;
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let Inst{22-20} = 0b001; // W = 0
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}
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} // isCodeGenOnly = 1
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//===----------------------------------------------------------------------===//
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// Load / store Instructions.
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@ -1683,8 +1681,7 @@ def STRHT: AI3sthpo<(outs GPR:$base_wb),
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// Load / store multiple Instructions.
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//
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
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reglist:$dsts, variable_ops),
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IndexModeNone, LdStMulFrm, IIC_iLoad_m,
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@ -1697,8 +1694,7 @@ def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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"$addr.addr = $wb", []>;
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} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p,
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reglist:$srcs, variable_ops),
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IndexModeNone, LdStMulFrm, IIC_iStore_m,
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@ -532,8 +532,7 @@ def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
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//
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// These require base address to be written back or one of the loaded regs.
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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def tLDM : T1I<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
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IIC_iLoad_m,
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@ -548,8 +547,7 @@ def tLDM_UPD : T1It<(outs tGPR:$wb),
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T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
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} // mayLoad, neverHasSideEffects = 1, hasExtraDefRegAllocReq
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
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isCodeGenOnly = 1 in
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
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def tSTM_UPD : T1It<(outs tGPR:$wb),
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(ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops),
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IIC_iStore_mu,
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@ -1241,8 +1241,7 @@ defm t2PLI : T2Ipl<1, 0, "pli">;
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// Load / store multiple Instructions.
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//
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
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reglist:$dsts, variable_ops), IIC_iLoad_m,
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"ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> {
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@ -1268,8 +1267,7 @@ def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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}
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} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p,
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reglist:$srcs, variable_ops), IIC_iStore_m,
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"stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> {
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@ -2431,7 +2429,7 @@ let Defs =
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// operand list.
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// FIXME: Should pc be an implicit operand like PICADD, etc?
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
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hasExtraDefRegAllocReq = 1 in
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def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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reglist:$dsts, variable_ops),
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IIC_iLoad_mBr,
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@ -72,8 +72,7 @@ def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
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// Load / store multiple Instructions.
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//
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
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def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
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variable_ops), IndexModeNone, IIC_fpLoad_m,
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"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
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@ -103,8 +102,7 @@ def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
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}
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} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
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variable_ops), IndexModeNone, IIC_fpStore_m,
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"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
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@ -562,7 +562,7 @@ let rb = 0 in {
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"src $dst, $src", [], IIAlu>;
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}
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let opcode=0x08, isCodeGenOnly=1 in {
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let opcode=0x08 in {
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def LEA_ADDI : TB<0x08, (outs GPR:$dst), (ins memri:$addr),
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"addi $dst, ${addr:stackloc}",
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[(set GPR:$dst, iaddr:$addr)], IIAlu>;
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@ -257,26 +257,27 @@ static bool IsAssemblerInstruction(StringRef Name,
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// this implies a constraint we would not honor.
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std::set<std::string> OperandNames;
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for (unsigned i = 1, e = Tokens.size(); i < e; ++i) {
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for (unsigned i = 1, e = Tokens.size(); i < e; ++i) {
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if (Tokens[i][0] == '$' &&
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Tokens[i].find(':') != StringRef::npos) {
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PrintError(CGI.TheDef->getLoc(),
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"instruction with operand modifier '" + Tokens[i].str() +
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"' not supported by asm matcher. Mark isCodeGenOnly!");
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throw std::string("ERROR: Invalid instruction");
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}
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if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) {
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DEBUG({
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if (Tokens[i][0] == '$' &&
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std::find(Tokens[i].begin(),
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Tokens[i].end(), ':') != Tokens[i].end()) {
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DEBUG({
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errs() << "warning: '" << Name << "': "
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<< "ignoring instruction; operand with attribute '"
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<< Tokens[i] << "'\n";
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});
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return false;
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}
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if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) {
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DEBUG({
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errs() << "warning: '" << Name << "': "
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<< "ignoring instruction with tied operand '"
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<< Tokens[i].str() << "'\n";
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});
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return false;
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}
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return false;
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}
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}
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return true;
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}
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@ -647,11 +648,13 @@ static std::string getEnumNameForToken(StringRef Str) {
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case '*': Res += "_STAR_"; break;
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case '%': Res += "_PCT_"; break;
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case ':': Res += "_COLON_"; break;
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default:
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if (isalnum(*it))
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if (isalnum(*it)) {
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Res += *it;
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else
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} else {
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Res += "_" + utostr((unsigned) *it) + "_";
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}
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}
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}
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@ -901,6 +904,14 @@ AsmMatcherInfo::AsmMatcherInfo(Record *asmParser)
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}
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void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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// Parse the instructions; we need to do this first so that we can gather the
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// singleton register classes.
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std::set<std::string> SingletonRegisterNames;
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const std::vector<const CodeGenInstruction*> &InstrList =
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Target.getInstructionsByEnumValue();
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// Build information about all of the AssemblerPredicates.
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std::vector<Record*> AllPredicates =
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Records.getAllDerivedDefinitions("Predicate");
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@ -920,16 +931,9 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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assert(FeatureNo < 32 && "Too many subtarget features!");
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}
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// Parse the instructions; we need to do this first so that we can gather the
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// singleton register classes.
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std::set<std::string> SingletonRegisterNames;
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const std::vector<const CodeGenInstruction*> &InstrList =
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Target.getInstructionsByEnumValue();
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for (unsigned i = 0, e = InstrList.size(); i != e; ++i) {
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const CodeGenInstruction &CGI = *InstrList[i];
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// If the tblgen -match-prefix option is specified (for tblgen hackers),
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// filter the set of instructions we consider.
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if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix))
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continue;
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@ -939,8 +943,7 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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II->Instr = &CGI;
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II->AsmString = FlattenVariants(CGI.AsmString, 0);
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// Remove comments from the asm string. We know that the asmstring only
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// has one line.
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// Remove comments from the asm string.
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if (!CommentDelimiter.empty()) {
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size_t Idx = StringRef(II->AsmString).find(CommentDelimiter);
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if (Idx != StringRef::npos)
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@ -952,7 +955,7 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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// Ignore instructions which shouldn't be matched.
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if (!IsAssemblerInstruction(CGI.TheDef->getName(), CGI, II->Tokens))
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continue;
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// Collect singleton registers, if used.
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for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) {
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if (!II->Tokens[i].startswith(RegisterPrefix))
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