mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Rewrite stack callee saved spills and restores to use push/pop instructions.
Remove movePastCSLoadStoreOps and associated code for simple pointer increments. Update routines that depended upon other opcodes for save/restore. Adjust all testcases accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119725 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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9fe010ecf8
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@ -197,6 +197,48 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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return NewMIs[0];
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}
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void
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ARMBaseInstrInfo::emitPushInst(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI, unsigned Opc,
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bool(*Func)(unsigned, bool)) const {
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MachineFunction &MF = *MBB.getParent();
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
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MIB.addReg(ARM::SP, getDefRegState(true));
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MIB.addReg(ARM::SP);
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AddDefaultPred(MIB);
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bool NumRegs = false;
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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if (!(Func)(Reg, Subtarget.isTargetDarwin())) continue;
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// Add the callee-saved register as live-in unless it's LR and
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// @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
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// then it's already added to the function and entry block live-in sets.
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bool isKill = true;
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if (Reg == ARM::LR) {
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if (MF.getFrameInfo()->isReturnAddressTaken() &&
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MF.getRegInfo().isLiveIn(Reg))
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isKill = false;
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}
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if (isKill)
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MBB.addLiveIn(Reg);
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NumRegs = true;
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MIB.addReg(Reg, getKillRegState(isKill));
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}
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// It's illegal to emit push instruction without operands.
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if (NumRegs)
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MBB.insert(MI, &*MIB);
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else
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MF.DeleteMachineInstr(MIB);
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}
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bool
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ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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@ -205,35 +247,79 @@ ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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if (CSI.empty())
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return false;
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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DebugLoc DL = MI->getDebugLoc();
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unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
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unsigned FltOpc = ARM::VSTMDDB_UPD;
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emitPushInst(MBB, MI, CSI, PushOpc, &isARMArea1Register);
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emitPushInst(MBB, MI, CSI, PushOpc, &isARMArea2Register);
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emitPushInst(MBB, MI, CSI, FltOpc, &isARMArea3Register);
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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bool isKill = true;
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// Add the callee-saved register as live-in unless it's LR and
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// @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
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// then it's already added to the function and entry block live-in sets.
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if (Reg == ARM::LR) {
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MachineFunction &MF = *MBB.getParent();
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if (MF.getFrameInfo()->isReturnAddressTaken() &&
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MF.getRegInfo().isLiveIn(Reg))
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isKill = false;
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}
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if (isKill)
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MBB.addLiveIn(Reg);
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// Insert the spill to the stack frame. The register is killed at the spill
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//
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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storeRegToStackSlot(MBB, MI, Reg, isKill,
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CSI[i].getFrameIdx(), RC, TRI);
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}
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return true;
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}
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void
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ARMBaseInstrInfo::emitPopInst(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI, unsigned Opc,
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bool isVarArg, bool(*Func)(unsigned, bool)) const {
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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DebugLoc DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
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MIB.addReg(ARM::SP, getDefRegState(true));
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MIB.addReg(ARM::SP);
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AddDefaultPred(MIB);
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bool NumRegs = false;
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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if (!(Func)(Reg, Subtarget.isTargetDarwin())) continue;
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if (Reg == ARM::LR && !isVarArg) {
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Reg = ARM::PC;
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unsigned Opc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
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(*MIB).setDesc(get(Opc));
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MI = MBB.erase(MI);
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}
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MIB.addReg(Reg, RegState::Define);
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NumRegs = true;
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}
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// It's illegal to emit pop instruction without operands.
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if (NumRegs)
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MBB.insert(MI, &*MIB);
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else
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MF.DeleteMachineInstr(MIB);
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}
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bool
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ARMBaseInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
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DebugLoc DL = MI->getDebugLoc();
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unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
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unsigned FltOpc = ARM::VLDMDIA_UPD;
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emitPopInst(MBB, MI, CSI, FltOpc, isVarArg, &isARMArea3Register);
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emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, &isARMArea2Register);
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emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, &isARMArea1Register);
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return true;
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}
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// Branch analysis.
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bool
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ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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@ -2195,7 +2281,7 @@ int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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case ARM::VSTMQIA:
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case ARM::VSTMQDB:
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return 2;
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}
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}
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}
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bool ARMBaseInstrInfo::
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@ -211,6 +211,21 @@ public:
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const;
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private:
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void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI, unsigned Opc,
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bool isVarArg, bool(*Func)(unsigned, bool)) const;
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void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI, unsigned Opc,
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bool(*Func)(unsigned, bool)) const;
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public:
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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@ -44,6 +44,45 @@ static inline bool isARMLowRegister(unsigned Reg) {
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}
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}
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/// isARMArea1Register - Returns true if the register is a low register (r0-r7)
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/// or a stack/pc register that we should push/pop.
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static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) {
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using namespace ARM;
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switch (Reg) {
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case R0: case R1: case R2: case R3:
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case R4: case R5: case R6: case R7:
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case LR: case SP: case PC:
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return true;
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case R8: case R9: case R10: case R11:
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// For darwin we want r7 and lr to be next to each other.
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return !isDarwin;
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default:
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return false;
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}
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}
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static inline bool isARMArea2Register(unsigned Reg, bool isDarwin) {
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using namespace ARM;
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switch (Reg) {
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case R8: case R9: case R10: case R11:
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// Darwin has this second area.
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return isDarwin;
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default:
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return false;
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}
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}
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static inline bool isARMArea3Register(unsigned Reg, bool isDarwin) {
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using namespace ARM;
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switch (Reg) {
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case D15: case D14: case D13: case D12:
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case D11: case D10: case D9: case D8:
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return true;
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default:
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return false;
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}
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}
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class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
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protected:
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const ARMBaseInstrInfo &TII;
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@ -20,43 +20,6 @@
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using namespace llvm;
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/// Move iterator past the next bunch of callee save load / store ops for
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/// the particular spill area (1: integer area 1, 2: integer area 2,
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/// 3: fp area, 0: don't care).
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static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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int Opc1, int Opc2, unsigned Area,
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const ARMSubtarget &STI) {
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while (MBBI != MBB.end() &&
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((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
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MBBI->getOperand(1).isFI()) {
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if (Area != 0) {
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bool Done = false;
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unsigned Category = 0;
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switch (MBBI->getOperand(0).getReg()) {
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case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
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case ARM::LR:
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Category = 1;
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break;
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case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
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Category = STI.isTargetDarwin() ? 2 : 1;
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break;
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case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
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case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
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Category = 3;
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break;
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default:
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Done = true;
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break;
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}
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if (Done || Category != Area)
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break;
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}
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++MBBI;
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}
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}
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static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
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for (unsigned i = 0; CSRegs[i]; ++i)
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if (Reg == CSRegs[i])
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@ -67,11 +30,21 @@ static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
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static bool isCSRestore(MachineInstr *MI,
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const ARMBaseInstrInfo &TII,
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const unsigned *CSRegs) {
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return ((MI->getOpcode() == (int)ARM::VLDRD ||
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MI->getOpcode() == (int)ARM::LDRi12 ||
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MI->getOpcode() == (int)ARM::t2LDRi12) &&
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MI->getOperand(1).isFI() &&
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isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
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// Integer spill area is handled with "pop".
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if (MI->getOpcode() == ARM::LDMIA_RET ||
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MI->getOpcode() == ARM::t2LDMIA_RET ||
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MI->getOpcode() == ARM::LDMIA_UPD ||
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MI->getOpcode() == ARM::t2LDMIA_UPD ||
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MI->getOpcode() == ARM::VLDMDIA_UPD) {
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// The first two operands are predicates. The last two are
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// imp-def and imp-use of SP. Check everything in between.
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for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
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if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
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return false;
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return true;
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}
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return false;
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}
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static void
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@ -154,11 +127,10 @@ void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
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DPRCSSize += 8;
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}
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}
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// Build the new SUBri to adjust SP for integer callee-save spill area 1.
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
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movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI);
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// Move past area 1.
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if (GPRCS1Size > 0) MBBI++;
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// Set FP to point to the stack slot that contains the previous FP.
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// For Darwin, FP is R7, which has now been stored in spill area 1.
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// Otherwise, if this is not Darwin, all the callee-saved registers go
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@ -172,14 +144,10 @@ void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
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.addFrameIndex(FramePtrSpillFI).addImm(0);
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AddDefaultCC(AddDefaultPred(MIB));
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}
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// Build the new SUBri to adjust SP for integer callee-save spill area 2.
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
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// Build the new SUBri to adjust SP for FP callee-save spill area.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
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// Move past area 2.
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if (GPRCS2Size > 0) MBBI++;
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// Determine starting offsets of spill areas.
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unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
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unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
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@ -191,7 +159,9 @@ void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
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AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
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AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
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movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
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// Move past area 3.
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if (DPRCSSize > 0) MBBI++;
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NumBytes = DPRCSOffset;
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if (NumBytes) {
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// Adjust SP after all the callee-save spills.
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@ -325,17 +295,10 @@ void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
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} else if (NumBytes)
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
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// Move SP to start of integer callee save spill area 2.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
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// Move SP to start of integer callee save spill area 1.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
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// Move SP to SP upon entry to the function.
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movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI);
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emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
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// Increment past our save areas.
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if (AFI->getDPRCalleeSavedAreaSize()) MBBI++;
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if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
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if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
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}
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if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
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@ -3,7 +3,7 @@
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; LDM instruction, was causing an assertion failure because the microop count
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; was being treated as an instruction count.
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; CHECK: ldmia
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; CHECK: push
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; CHECK: ldmia
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; CHECK: ldmia
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; CHECK: ldmia
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@ -4,8 +4,8 @@
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define i64 @t(i64 %a) nounwind readonly {
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entry:
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; CHECK: str lr, [sp, #-4]!
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; CHECK: ldr lr, [sp], #4
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; CHECK: push {lr}
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; CHECK: ldmia sp!, {pc}
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%0 = load i64** @b, align 4
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%1 = load i64* %0, align 4
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%2 = mul i64 %1, %a
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@ -39,7 +39,7 @@ entry:
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; CHECK: ittt eq
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; CHECK: moveq r0
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; CHECK-NOT: LBB0_
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; CHECK: ldreq
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; CHECK: popeq
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; CHECK: popeq
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switch i32 undef, label %bb7 [
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i32 37, label %bb43
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