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Enable machine code verification in the entire code generator.

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Some targets still mess up the liveness information, but that isn't
verified after MRI->invalidateLiveness().

The verifier can still check other useful things like register classes
and CFG, so it should be enabled after all passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153615 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-03-28 23:54:28 +00:00
parent 78811669d5
commit 8b4c502098
3 changed files with 5 additions and 15 deletions
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5
include/llvm/CodeGen/Passes.h
View File

@ -223,11 +223,6 @@ protected:
/// regalloc pass. /// regalloc pass.
FunctionPass *createRegAllocPass(bool Optimized); FunctionPass *createRegAllocPass(bool Optimized);
/// printNoVerify - Add a pass to dump the machine function, if debugging is
/// enabled.
///
void printNoVerify(const char *Banner) const;
/// printAndVerify - Add a pass to dump then verify the machine function, if /// printAndVerify - Add a pass to dump then verify the machine function, if
/// those steps are enabled. /// those steps are enabled.
/// ///

11
lib/CodeGen/Passes.cpp
View File

@ -272,11 +272,6 @@ AnalysisID TargetPassConfig::addPass(char &ID) {
return FinalID; return FinalID;
} }
void TargetPassConfig::printNoVerify(const char *Banner) const {
if (TM->shouldPrintMachineCode())
PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
}
void TargetPassConfig::printAndVerify(const char *Banner) const { void TargetPassConfig::printAndVerify(const char *Banner) const {
if (TM->shouldPrintMachineCode()) if (TM->shouldPrintMachineCode())
PM.add(createMachineFunctionPrinterPass(dbgs(), Banner)); PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
@ -403,7 +398,7 @@ void TargetPassConfig::addMachinePasses() {
// Second pass scheduler. // Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
addPass(PostRASchedulerID); addPass(PostRASchedulerID);
printNoVerify("After PostRAScheduler"); printAndVerify("After PostRAScheduler");
} }
// GC // GC
@ -416,7 +411,7 @@ void TargetPassConfig::addMachinePasses() {
addBlockPlacement(); addBlockPlacement();
if (addPreEmitPass()) if (addPreEmitPass())
printNoVerify("After PreEmit passes"); printAndVerify("After PreEmit passes");
} }
/// Add passes that optimize machine instructions in SSA form. /// Add passes that optimize machine instructions in SSA form.
@ -628,6 +623,6 @@ void TargetPassConfig::addBlockPlacement() {
if (EnableBlockPlacementStats) if (EnableBlockPlacementStats)
addPass(MachineBlockPlacementStatsID); addPass(MachineBlockPlacementStatsID);
printNoVerify("After machine block placement."); printAndVerify("After machine block placement.");
} }
} }

4
lib/Target/PTX/PTXTargetMachine.cpp
View File

@ -152,10 +152,10 @@ bool PTXPassConfig::addPostRegAlloc() {
/// Add passes that optimize machine instructions after register allocation. /// Add passes that optimize machine instructions after register allocation.
void PTXPassConfig::addMachineLateOptimization() { void PTXPassConfig::addMachineLateOptimization() {
if (addPass(BranchFolderPassID) != &NoPassID) if (addPass(BranchFolderPassID) != &NoPassID)
printNoVerify("After BranchFolding"); printAndVerify("After BranchFolding");
if (addPass(TailDuplicateID) != &NoPassID) if (addPass(TailDuplicateID) != &NoPassID)
printNoVerify("After TailDuplicate"); printAndVerify("After TailDuplicate");
} }
bool PTXPassConfig::addPreEmitPass() { bool PTXPassConfig::addPreEmitPass() {