mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Lower select with custom inserted and make condjumps generic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70744 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
ed1a51af37
commit
8b528e52ee
@ -51,6 +51,7 @@ namespace {
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const char* Modifier = 0);
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void printSrcMemOperand(const MachineInstr *MI, int OpNum,
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const char* Modifier = 0);
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void printCCOperand(const MachineInstr *MI, int OpNum);
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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void printMachineInstruction(const MachineInstr * MI);
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bool runOnMachineFunction(MachineFunction &F);
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@ -182,3 +183,30 @@ void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum,
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assert(0 && "Unsupported memory operand");
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}
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void MSP430AsmPrinter::printCCOperand(const MachineInstr *MI, int OpNum) {
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unsigned CC = MI->getOperand(OpNum).getImm();
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switch (CC) {
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default:
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assert(0 && "Unsupported CC code");
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break;
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case MSP430::COND_E:
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O << 'e';
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break;
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case MSP430::COND_NE:
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O << "ne";
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break;
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case MSP430::COND_HS:
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O << "hs";
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break;
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case MSP430::COND_LO:
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O << "lo";
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break;
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case MSP430::COND_GE:
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O << "ge";
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break;
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case MSP430::COND_L:
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O << 'l';
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break;
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}
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}
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@ -72,8 +72,11 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
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setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::SETCC, MVT::i8 , Custom);
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setOperationAction(ISD::SETCC, MVT::i16 , Custom);
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setOperationAction(ISD::SETCC, MVT::i8, Custom);
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setOperationAction(ISD::SETCC, MVT::i16, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT, MVT::i8, Custom);
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setOperationAction(ISD::SELECT, MVT::i16, Custom);
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}
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SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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@ -85,6 +88,7 @@ SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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case ISD::SELECT: return LowerSELECT(Op, DAG);
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default:
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assert(0 && "unimplemented operand");
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return SDValue();
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@ -517,6 +521,40 @@ SDValue MSP430TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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Chain, Dest, CC, Cond);
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}
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SDValue MSP430TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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SDValue Cond = Op.getOperand(0);
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SDValue TrueV = Op.getOperand(1);
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SDValue FalseV = Op.getOperand(2);
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DebugLoc dl = Op.getDebugLoc();
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SDValue CC;
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// Lower condition if not lowered yet
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if (Cond.getOpcode() == ISD::SETCC)
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Cond = LowerSETCC(Cond, DAG);
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// If condition flag is set by a MSP430ISD::CMP, then use it as the condition
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// setting operand in place of the MSP430ISD::SETCC.
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if (Cond.getOpcode() == MSP430ISD::SETCC) {
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CC = Cond.getOperand(0);
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Cond = Cond.getOperand(1);
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TrueV = Cond.getOperand(0);
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FalseV = Cond.getOperand(1);
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} else {
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CC = DAG.getConstant(MSP430::COND_NE, MVT::i16);
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Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16,
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Cond, DAG.getConstant(0, MVT::i16));
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}
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SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
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SmallVector<SDValue, 4> Ops;
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Ops.push_back(TrueV);
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Ops.push_back(FalseV);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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return DAG.getNode(MSP430ISD::SELECT, dl, VTs, &Ops[0], Ops.size());
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}
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const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return NULL;
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@ -527,5 +565,69 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MSP430ISD::BRCOND: return "MSP430ISD::BRCOND";
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case MSP430ISD::CMP: return "MSP430ISD::CMP";
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case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
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case MSP430ISD::SELECT: return "MSP430ISD::SELECT";
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}
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}
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//===----------------------------------------------------------------------===//
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// Other Lowering Code
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//===----------------------------------------------------------------------===//
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MachineBasicBlock*
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MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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assert((MI->getOpcode() == MSP430::Select16) &&
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"Unexpected instr type to insert");
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// To "insert" a SELECT instruction, we actually have to insert the diamond
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// control-flow pattern. The incoming instruction knows the destination vreg
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// to set, the condition code register to branch on, the true/false values to
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// select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator I = BB;
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++I;
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// thisMBB:
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// ...
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// TrueVal = ...
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// cmpTY ccX, r1, r2
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// jCC copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
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BuildMI(BB, dl, TII.get(MSP430::JCC))
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.addMBB(copy1MBB)
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.addImm(MI->getOperand(3).getImm());
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F->insert(I, copy0MBB);
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F->insert(I, copy1MBB);
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// Update machine-CFG edges by transferring all successors of the current
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// block to the new block which will contain the Phi node for the select.
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copy1MBB->transferSuccessors(BB);
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// Next, add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(copy1MBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to copy1MBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(copy1MBB);
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// copy1MBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = copy1MBB;
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BuildMI(BB, dl, TII.get(MSP430::PHI),
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MI->getOperand(0).getReg())
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.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
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F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
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return BB;
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}
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@ -49,7 +49,11 @@ namespace llvm {
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/// is the block to branch if condition is true, operand 2 is the
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/// condition code, and operand 3 is the flag operand produced by a CMP
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/// instruction.
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BRCOND
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BRCOND,
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/// SELECT. Operand 0 and operand 1 are selection variable, operand 3 is
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/// condition code and operand 4 is flag operand.
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SELECT
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};
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}
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@ -77,6 +81,7 @@ namespace llvm {
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
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unsigned CC);
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@ -84,6 +89,8 @@ namespace llvm {
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CallSDNode *TheCall,
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unsigned CallingConv, SelectionDAG &DAG);
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MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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private:
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const MSP430Subtarget &Subtarget;
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@ -22,8 +22,7 @@ namespace llvm {
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class MSP430TargetMachine;
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namespace MSP430 {
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// MSP430 specific condition code. These correspond to MSP430_*_COND in
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// MSP430InstrInfo.td. They must be kept in synch.
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// MSP430 specific condition code.
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enum CondCode {
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COND_E = 0, // aka COND_Z
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COND_NE = 1, // aka COND_NZ
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@ -31,6 +31,8 @@ def SDT_MSP430SetCC : SDTypeProfile<1, 2, [SDTCisVT<0, i8>,
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def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def SDT_MSP430BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
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SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
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def SDT_MSP430Select : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisVT<3, i8>, SDTCisVT<4, i16>]>;
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//===----------------------------------------------------------------------===//
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// MSP430 Specific Node Definitions.
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@ -52,6 +54,7 @@ def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
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def MSP430setcc : SDNode<"MSP430ISD::SETCC", SDT_MSP430SetCC>;
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def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp>;
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def MSP430brcond : SDNode<"MSP430ISD::BRCOND", SDT_MSP430BrCond, [SDNPHasChain]>;
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def MSP430select : SDNode<"MSP430ISD::SELECT", SDT_MSP430Select>;
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//===----------------------------------------------------------------------===//
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// MSP430 Operand Definitions.
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@ -71,6 +74,11 @@ def memdst : Operand<i16> {
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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// Operand for printing out a condition code.
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def cc : Operand<i8> {
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let PrintMethod = "printCCOperand";
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}
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//===----------------------------------------------------------------------===//
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// MSP430 Complex Pattern Definitions.
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//===----------------------------------------------------------------------===//
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@ -82,15 +90,6 @@ def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
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def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
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def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
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// MSP430 specific condition code. These correspond to CondCode in
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// MSP430InstrInfo.h. They must be kept in synch.
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def MSP430_COND_E : PatLeaf<(i8 0)>; // aka COND_Z
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def MSP430_COND_NE : PatLeaf<(i8 1)>; // aka COND_NZ
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def MSP430_COND_HS : PatLeaf<(i8 2)>; // aka COND_C
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def MSP430_COND_LO : PatLeaf<(i8 3)>; // aka COND_NC
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def MSP430_COND_GE : PatLeaf<(i8 4)>;
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def MSP430_COND_L : PatLeaf<(i8 5)>;
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//===----------------------------------------------------------------------===//
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// Instruction list..
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@ -108,6 +107,12 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
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[(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
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}
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let usesCustomDAGSchedInserter = 1 in {
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def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cc),
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"# Select16 PSEUDO",
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[(set GR16:$dst,
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(MSP430select GR16:$src1, GR16:$src2, imm:$cc, SRW))]>;
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}
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let neverHasSideEffects = 1 in
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def NOP : Pseudo<(outs), (ins), "nop", []>;
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@ -123,18 +128,9 @@ let isReturn = 1, isTerminator = 1 in {
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// Conditional branches
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let isBranch = 1, isTerminator = 1, Uses = [SRW] in {
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def JE : Pseudo<(outs), (ins brtarget:$dst), "je\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_E, SRW)]>;
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def JNE : Pseudo<(outs), (ins brtarget:$dst), "jne\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_NE, SRW)]>;
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def JHS : Pseudo<(outs), (ins brtarget:$dst), "jhs\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_HS, SRW)]>;
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def JLO : Pseudo<(outs), (ins brtarget:$dst), "jlo\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_LO, SRW)]>;
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def JGE : Pseudo<(outs), (ins brtarget:$dst), "jge\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_GE, SRW)]>;
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def JL : Pseudo<(outs), (ins brtarget:$dst), "jl\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_L, SRW)]>;
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def JCC : Pseudo<(outs), (ins brtarget:$dst, cc:$cc),
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"j$cc $dst",
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[(MSP430brcond bb:$dst, imm:$cc, SRW)]>;
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} // Uses = [SRW]
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//===----------------------------------------------------------------------===//
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@ -656,17 +652,17 @@ def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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// Integer comparisons
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let Defs = [SRW] in {
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def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
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"cmp.b\t{$src2, $src1|$src1, $src2}",
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"cmp.b\t{$src1, $src2}",
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[(MSP430cmp GR8:$src1, GR8:$src2), (implicit SRW)]>;
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def CMP16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
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"cmp.w\t{$src2, $src1|$src1, $src2}",
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"cmp.w\t{$src1, $src2}",
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[(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
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def CMP8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2),
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"cmp.b\t{$src2, $src1|$src1, $src2}",
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"cmp.b\t{$src1, $src2}",
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[(MSP430cmp GR8:$src1, imm:$src2), (implicit SRW)]>;
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def CMP16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
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"cmp.w\t{$src2, $src1|$src1, $src2}",
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"cmp.w\t{$src1, $src2}",
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[(MSP430cmp GR16:$src1, imm:$src2), (implicit SRW)]>;
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def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
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