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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
Add first draft for conditions, conditional branches, etc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70743 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
6e4f62790b
commit
ed1a51af37
@ -70,6 +70,10 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
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setOperationAction(ISD::SRA, MVT::i16, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::SETCC, MVT::i8 , Custom);
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setOperationAction(ISD::SETCC, MVT::i16 , Custom);
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}
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SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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@ -79,6 +83,8 @@ SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::CALL: return LowerCALL(Op, DAG);
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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default:
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assert(0 && "unimplemented operand");
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return SDValue();
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@ -437,6 +443,80 @@ SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
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getPointerTy(), Result);
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}
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MVT MSP430TargetLowering::getSetCCResultType(MVT VT) const {
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return MVT::i8;
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}
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SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
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assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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DebugLoc dl = Op.getDebugLoc();
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
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// FIXME: Handle bittests someday
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assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
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// FIXME: Handle jump negative someday
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unsigned TargetCC = 0;
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switch (CC) {
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default: assert(0 && "Invalid integer condition!");
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case ISD::SETEQ:
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TargetCC = MSP430::COND_E; // aka COND_Z
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break;
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case ISD::SETNE:
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TargetCC = MSP430::COND_NE; // aka COND_NZ
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break;
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case ISD::SETULE:
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std::swap(LHS, RHS); // FALLTHROUGH
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case ISD::SETUGE:
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TargetCC = MSP430::COND_HS; // aka COND_C
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break;
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case ISD::SETUGT:
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std::swap(LHS, RHS); // FALLTHROUGH
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case ISD::SETULT:
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TargetCC = MSP430::COND_LO; // aka COND_NC
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break;
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case ISD::SETLE:
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std::swap(LHS, RHS); // FALLTHROUGH
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case ISD::SETGE:
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TargetCC = MSP430::COND_GE;
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break;
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case ISD::SETGT:
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std::swap(LHS, RHS); // FALLTHROUGH
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case ISD::SETLT:
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TargetCC = MSP430::COND_L;
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break;
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}
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SDValue Cond = DAG.getNode(MSP430ISD::CMP, dl, MVT::i16, LHS, RHS);
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return DAG.getNode(MSP430ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(TargetCC, MVT::i8), Cond);
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}
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SDValue MSP430TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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SDValue Chain = Op.getOperand(0);
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SDValue Cond = Op.getOperand(1);
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SDValue Dest = Op.getOperand(2);
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DebugLoc dl = Op.getDebugLoc();
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SDValue CC;
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// Lower condition if not lowered yet
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if (Cond.getOpcode() == ISD::SETCC)
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Cond = LowerSETCC(Cond, DAG);
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// If condition flag is set by a MSP430ISD::CMP, then use it as the condition
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// setting operand in place of the MSP430ISD::SETCC.
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if (Cond.getOpcode() == MSP430ISD::SETCC) {
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CC = Cond.getOperand(0);
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Cond = Cond.getOperand(1);
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} else
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assert(0 && "Unimplemented condition!");
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return DAG.getNode(MSP430ISD::BRCOND, dl, Op.getValueType(),
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Chain, Dest, CC, Cond);
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}
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const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return NULL;
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@ -444,5 +524,8 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MSP430ISD::RRA: return "MSP430ISD::RRA";
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case MSP430ISD::CALL: return "MSP430ISD::CALL";
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case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
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case MSP430ISD::BRCOND: return "MSP430ISD::BRCOND";
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case MSP430ISD::CMP: return "MSP430ISD::CMP";
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case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
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}
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}
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@ -36,7 +36,20 @@ namespace llvm {
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/// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
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/// and TargetGlobalAddress.
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Wrapper
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Wrapper,
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/// CMP - Compare instruction.
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CMP,
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/// SetCC. Operand 0 is condition code, and operand 1 is the flag
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/// operand produced by a CMP instruction.
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SETCC,
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/// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
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/// is the block to branch if condition is true, operand 2 is the
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/// condition code, and operand 3 is the flag operand produced by a CMP
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/// instruction.
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BRCOND
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};
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}
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@ -54,12 +67,16 @@ namespace llvm {
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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virtual MVT getSetCCResultType(MVT VT) const;
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SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
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SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
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SDValue LowerShifts(SDValue Op, SelectionDAG &DAG);
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
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unsigned CC);
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@ -21,6 +21,21 @@ namespace llvm {
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class MSP430TargetMachine;
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namespace MSP430 {
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// MSP430 specific condition code. These correspond to MSP430_*_COND in
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// MSP430InstrInfo.td. They must be kept in synch.
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enum CondCode {
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COND_E = 0, // aka COND_Z
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COND_NE = 1, // aka COND_NZ
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COND_HS = 2, // aka COND_C
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COND_LO = 3, // aka COND_NC
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COND_GE = 4,
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COND_L = 5,
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COND_INVALID
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};
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}
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class MSP430InstrInfo : public TargetInstrInfoImpl {
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const MSP430RegisterInfo RI;
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MSP430TargetMachine &TM;
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@ -26,6 +26,11 @@ def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
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def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
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def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
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def SDT_MSP430SetCC : SDTypeProfile<1, 2, [SDTCisVT<0, i8>,
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SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
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def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def SDT_MSP430BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
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SDTCisVT<1, i8>, SDTCisVT<2, i16>]>;
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//===----------------------------------------------------------------------===//
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// MSP430 Specific Node Definitions.
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@ -43,7 +48,10 @@ def MSP430callseq_start :
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def MSP430callseq_end :
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SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
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def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>;
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def MSP430setcc : SDNode<"MSP430ISD::SETCC", SDT_MSP430SetCC>;
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def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp>;
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def MSP430brcond : SDNode<"MSP430ISD::BRCOND", SDT_MSP430BrCond, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// MSP430 Operand Definitions.
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@ -60,6 +68,9 @@ def memdst : Operand<i16> {
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let MIOperandInfo = (ops GR16, i16imm);
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}
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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//===----------------------------------------------------------------------===//
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// MSP430 Complex Pattern Definitions.
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//===----------------------------------------------------------------------===//
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@ -71,6 +82,15 @@ def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
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def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
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def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
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// MSP430 specific condition code. These correspond to CondCode in
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// MSP430InstrInfo.h. They must be kept in synch.
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def MSP430_COND_E : PatLeaf<(i8 0)>; // aka COND_Z
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def MSP430_COND_NE : PatLeaf<(i8 1)>; // aka COND_NZ
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def MSP430_COND_HS : PatLeaf<(i8 2)>; // aka COND_C
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def MSP430_COND_LO : PatLeaf<(i8 3)>; // aka COND_NC
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def MSP430_COND_GE : PatLeaf<(i8 4)>;
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def MSP430_COND_L : PatLeaf<(i8 5)>;
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//===----------------------------------------------------------------------===//
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// Instruction list..
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@ -92,11 +112,31 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
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let neverHasSideEffects = 1 in
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def NOP : Pseudo<(outs), (ins), "nop", []>;
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions...
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//
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// FIXME: Provide proper encoding!
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let isReturn = 1, isTerminator = 1 in {
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def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
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}
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// Conditional branches
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let isBranch = 1, isTerminator = 1, Uses = [SRW] in {
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def JE : Pseudo<(outs), (ins brtarget:$dst), "je\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_E, SRW)]>;
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def JNE : Pseudo<(outs), (ins brtarget:$dst), "jne\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_NE, SRW)]>;
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def JHS : Pseudo<(outs), (ins brtarget:$dst), "jhs\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_HS, SRW)]>;
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def JLO : Pseudo<(outs), (ins brtarget:$dst), "jlo\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_LO, SRW)]>;
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def JGE : Pseudo<(outs), (ins brtarget:$dst), "jge\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_GE, SRW)]>;
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def JL : Pseudo<(outs), (ins brtarget:$dst), "jl\t$dst",
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[(MSP430brcond bb:$dst, MSP430_COND_L, SRW)]>;
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} // Uses = [SRW]
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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@ -613,6 +653,51 @@ def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
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} // isTwoAddress = 1
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// Integer comparisons
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let Defs = [SRW] in {
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def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
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"cmp.b\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp GR8:$src1, GR8:$src2), (implicit SRW)]>;
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def CMP16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
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"cmp.w\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
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def CMP8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2),
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"cmp.b\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp GR8:$src1, imm:$src2), (implicit SRW)]>;
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def CMP16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
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"cmp.w\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp GR16:$src1, imm:$src2), (implicit SRW)]>;
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def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
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"cmp.b\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;
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def CMP16rm : Pseudo<(outs), (ins GR16:$src1, memsrc:$src2),
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"cmp.w\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp GR16:$src1, (load addr:$src2)), (implicit SRW)]>;
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def CMP8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
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"cmp.b\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp (load addr:$src1), GR8:$src2), (implicit SRW)]>;
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def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
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"cmp.w\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
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def CMP8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2),
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"cmp.b\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp (load addr:$src1), (i8 imm:$src2)), (implicit SRW)]>;
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def CMP16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2),
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"cmp.w\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp (load addr:$src1), (i16 imm:$src2)), (implicit SRW)]>;
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def CMP8mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
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"cmp.b\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp (load addr:$src1), (i8 (load addr:$src2))), (implicit SRW)]>;
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def CMP16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
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"cmp.w\t{$src2, $src1|$src1, $src2}",
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[(MSP430cmp (load addr:$src1), (i16 (load addr:$src2))), (implicit SRW)]>;
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} // Defs = [SRW]
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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