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added a chain output

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24306 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-11-11 22:48:54 +00:00
parent c2c64fd3c6
commit 8b91c77385
2 changed files with 13 additions and 2 deletions
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3
include/llvm/CodeGen/SelectionDAGNodes.h
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@ -308,6 +308,9 @@ namespace ISD {
PCMARKER,
// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
// The only operand is a chain and a value and a chain are produced. The
// value is the contents of the architecture specific cycle counter like
// register (or other high accuracy low latency clock source)
READCYCLECOUNTER,
// READPORT, WRITEPORT, READIO, WRITEIO - These correspond to the LLVM

12
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -804,9 +804,17 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::readcyclecounter:
setValue(&I, DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, getRoot()));
case Intrinsic::readcyclecounter: {
std::vector<MVT::ValueType> VTs;
VTs.push_back(MVT::i64);
VTs.push_back(MVT::Other);
std::vector<SDOperand> Ops;
Ops.push_back(getRoot());
SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
}
case Intrinsic::cttz:
setValue(&I, DAG.getNode(ISD::CTTZ,
getValue(I.getOperand(1)).getValueType(),