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https://github.com/c64scene-ar/llvm-6502.git
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AArch64: improve handling & modelling of FP_TO_XINT nodes.
There's probably no acatual change in behaviour here, just updating the LowerFP_TO_INT function to be more similar to the reverse implementation and updating costs to current CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210985 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1387,24 +1387,22 @@ static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
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EVT InVT = Op.getOperand(0).getValueType();
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EVT VT = Op.getValueType();
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// FP_TO_XINT conversion from the same type are legal.
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if (VT.getSizeInBits() == InVT.getSizeInBits())
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return Op;
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if (InVT == MVT::v2f64 || InVT == MVT::v4f32) {
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if (VT.getSizeInBits() < InVT.getSizeInBits()) {
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SDLoc dl(Op);
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SDValue Cv =
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DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
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Op.getOperand(0));
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
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} else if (InVT == MVT::v2f32) {
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}
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if (VT.getSizeInBits() > InVT.getSizeInBits()) {
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SDLoc dl(Op);
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SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
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return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
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}
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// Type changing conversions are illegal.
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return SDValue();
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return Op;
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}
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SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
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@ -315,8 +315,10 @@ unsigned AArch64TTI::getCastInstrCost(unsigned Opcode, Type *Dst,
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// Complex: to v2f32
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
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// Complex: to v4f32
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
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@ -341,12 +343,27 @@ unsigned AArch64TTI::getCastInstrCost(unsigned Opcode, Type *Dst,
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{ ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
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// Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
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{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
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{ ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
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{ ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 },
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// Complex, from v4f32: legal type is v4i16, 1 narrowing => ~2
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{ ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
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{ ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
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// Complex, from v2f64: legal type is v2i32, 1 narrowing => ~2.
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 },
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{ ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 2 },
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};
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int Idx = ConvertCostTableLookup<MVT>(
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@ -1,24 +1,141 @@
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; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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; CHECK: fptosi_1
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; CHECK: fcvtzs.2d
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; CHECK: xtn.2s
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; CHECK: ret
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define void @fptosi_1(<2 x double> %in, <2 x i32>* %addr) nounwind noinline ssp {
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entry:
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%0 = fptosi <2 x double> %in to <2 x i32>
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store <2 x i32> %0, <2 x i32>* %addr, align 8
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ret void
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define <2 x i64> @test_v2f32_to_signed_v2i64(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_signed_v2i64:
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; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
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; CHECK: fcvtzs.2d v0, [[VAL64]]
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%val = fptosi <2 x float> %in to <2 x i64>
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ret <2 x i64> %val
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}
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; CHECK: fptoui_1
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; CHECK: fcvtzu.2d
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; CHECK: xtn.2s
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; CHECK: ret
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define void @fptoui_1(<2 x double> %in, <2 x i32>* %addr) nounwind noinline ssp {
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entry:
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%0 = fptoui <2 x double> %in to <2 x i32>
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store <2 x i32> %0, <2 x i32>* %addr, align 8
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ret void
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define <2 x i64> @test_v2f32_to_unsigned_v2i64(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_unsigned_v2i64:
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; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
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; CHECK: fcvtzu.2d v0, [[VAL64]]
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%val = fptoui <2 x float> %in to <2 x i64>
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ret <2 x i64> %val
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}
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define <2 x i16> @test_v2f32_to_signed_v2i16(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_signed_v2i16:
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; CHECK: fcvtzs.2s v0, v0
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%val = fptosi <2 x float> %in to <2 x i16>
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ret <2 x i16> %val
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}
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define <2 x i16> @test_v2f32_to_unsigned_v2i16(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_unsigned_v2i16:
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; CHECK: fcvtzs.2s v0, v0
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%val = fptoui <2 x float> %in to <2 x i16>
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ret <2 x i16> %val
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}
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define <2 x i8> @test_v2f32_to_signed_v2i8(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_signed_v2i8:
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; CHECK: fcvtzs.2s v0, v0
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%val = fptosi <2 x float> %in to <2 x i8>
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ret <2 x i8> %val
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}
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define <2 x i8> @test_v2f32_to_unsigned_v2i8(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_unsigned_v2i8:
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; CHECK: fcvtzs.2s v0, v0
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%val = fptoui <2 x float> %in to <2 x i8>
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ret <2 x i8> %val
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}
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define <4 x i16> @test_v4f32_to_signed_v4i16(<4 x float> %in) {
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; CHECK-LABEL: test_v4f32_to_signed_v4i16:
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; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.4h v0, [[VAL64]]
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%val = fptosi <4 x float> %in to <4 x i16>
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ret <4 x i16> %val
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}
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define <4 x i16> @test_v4f32_to_unsigned_v4i16(<4 x float> %in) {
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; CHECK-LABEL: test_v4f32_to_unsigned_v4i16:
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; CHECK: fcvtzu.4s [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.4h v0, [[VAL64]]
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%val = fptoui <4 x float> %in to <4 x i16>
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ret <4 x i16> %val
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}
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define <4 x i8> @test_v4f32_to_signed_v4i8(<4 x float> %in) {
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; CHECK-LABEL: test_v4f32_to_signed_v4i8:
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; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.4h v0, [[VAL64]]
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%val = fptosi <4 x float> %in to <4 x i8>
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ret <4 x i8> %val
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}
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define <4 x i8> @test_v4f32_to_unsigned_v4i8(<4 x float> %in) {
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; CHECK-LABEL: test_v4f32_to_unsigned_v4i8:
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; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.4h v0, [[VAL64]]
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%val = fptoui <4 x float> %in to <4 x i8>
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ret <4 x i8> %val
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}
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define <2 x i32> @test_v2f64_to_signed_v2i32(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_signed_v2i32:
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; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptosi <2 x double> %in to <2 x i32>
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ret <2 x i32> %val
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}
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define <2 x i32> @test_v2f64_to_unsigned_v2i32(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_unsigned_v2i32:
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; CHECK: fcvtzu.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptoui <2 x double> %in to <2 x i32>
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ret <2 x i32> %val
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}
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define <2 x i16> @test_v2f64_to_signed_v2i16(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_signed_v2i16:
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; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptosi <2 x double> %in to <2 x i16>
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ret <2 x i16> %val
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}
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define <2 x i16> @test_v2f64_to_unsigned_v2i16(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_unsigned_v2i16:
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; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptoui <2 x double> %in to <2 x i16>
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ret <2 x i16> %val
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}
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define <2 x i8> @test_v2f64_to_signed_v2i8(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_signed_v2i8:
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; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptosi <2 x double> %in to <2 x i8>
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ret <2 x i8> %val
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}
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define <2 x i8> @test_v2f64_to_unsigned_v2i8(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_unsigned_v2i8:
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; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptoui <2 x double> %in to <2 x i8>
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ret <2 x i8> %val
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}
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