mirror of
https://github.com/c64scene-ar/llvm-6502.git
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AArch64: improve vector [su]itofp handling.
This somehow got missed in the AArch64 merge, so should fix a performance regression since 3.4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210984 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
e12d893d7a
commit
94fe5c1fe2
@ -1440,32 +1440,23 @@ static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
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SDValue In = Op.getOperand(0);
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EVT InVT = In.getValueType();
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// v2i32 to v2f32 is legal.
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if (VT == MVT::v2f32 && InVT == MVT::v2i32)
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return Op;
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// This function only handles v2f64 outputs.
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if (VT == MVT::v2f64) {
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// Extend the input argument to a v2i64 that we can feed into the
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// floating point conversion. Zero or sign extend based on whether
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// we're doing a signed or unsigned float conversion.
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unsigned Opc =
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Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
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assert(Op.getNumOperands() == 1 && "FP conversions take one argument");
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SDValue Promoted = DAG.getNode(Opc, dl, MVT::v2i64, Op.getOperand(0));
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return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Promoted);
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if (VT.getSizeInBits() < InVT.getSizeInBits()) {
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MVT CastVT =
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MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
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InVT.getVectorNumElements());
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In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
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return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
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}
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// Scalarize v2i64 to v2f32 conversions.
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std::vector<SDValue> BuildVectorOps;
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for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
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SDValue Sclr = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, In,
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DAG.getConstant(i, MVT::i64));
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Sclr = DAG.getNode(Op->getOpcode(), dl, MVT::f32, Sclr);
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BuildVectorOps.push_back(Sclr);
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if (VT.getSizeInBits() > InVT.getSizeInBits()) {
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unsigned CastOpc =
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Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
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EVT CastVT = VT.changeVectorElementTypeToInteger();
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In = DAG.getNode(CastOpc, dl, CastVT, In);
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return DAG.getNode(Op.getOpcode(), dl, VT, In);
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}
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return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, BuildVectorOps);
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return Op;
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}
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SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
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@ -306,28 +306,47 @@ unsigned AArch64TTI::getCastInstrCost(unsigned Opcode, Type *Dst,
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static const TypeConversionCostTblEntry<MVT> ConversionTbl[] = {
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// LowerVectorINT_TO_FP:
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 1 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 1 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 1 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 1 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
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// Complex: to v2f32
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
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// Complex: to v4f32
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
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// Complex: to v2f64
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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// LowerVectorFP_TO_INT
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
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{ ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
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{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 },
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 4 },
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{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 4 },
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{ ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 },
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{ ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 4 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 4 },
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{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 4 },
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
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{ ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
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};
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int Idx = ConvertCostTableLookup<MVT>(
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@ -1,29 +0,0 @@
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; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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define <2 x double> @f1(<2 x i32> %v) nounwind readnone {
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; CHECK-LABEL: f1:
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; CHECK: sshll.2d v0, v0, #0
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; CHECK-NEXT: scvtf.2d v0, v0
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; CHECK-NEXT: ret
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%conv = sitofp <2 x i32> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @f2(<2 x i32> %v) nounwind readnone {
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; CHECK-LABEL: f2:
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; CHECK: ushll.2d v0, v0, #0
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; CHECK-NEXT: ucvtf.2d v0, v0
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; CHECK-NEXT: ret
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%conv = uitofp <2 x i32> %v to <2 x double>
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ret <2 x double> %conv
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}
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; CHECK: autogen_SD19655
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; CHECK: scvtf
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; CHECK: ret
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define void @autogen_SD19655(<2 x i64>* %addr, <2 x float>* %addrfloat) {
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%T = load <2 x i64>* %addr
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%F = sitofp <2 x i64> %T to <2 x float>
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store <2 x float> %F, <2 x float>* %addrfloat
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ret void
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}
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164
test/CodeGen/AArch64/complex-int-to-fp.ll
Normal file
164
test/CodeGen/AArch64/complex-int-to-fp.ll
Normal file
@ -0,0 +1,164 @@
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; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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; CHECK: autogen_SD19655
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; CHECK: scvtf
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; CHECK: ret
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define void @autogen_SD19655(<2 x i64>* %addr, <2 x float>* %addrfloat) {
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%T = load <2 x i64>* %addr
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%F = sitofp <2 x i64> %T to <2 x float>
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store <2 x float> %F, <2 x float>* %addrfloat
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ret void
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}
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define <2 x double> @test_signed_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i32_to_v2f64:
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; CHECK: sshll.2d [[VAL64:v[0-9]+]], v0, #0
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; CHECK-NEXT: scvtf.2d v0, [[VAL64]]
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; CHECK-NEXT: ret
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%conv = sitofp <2 x i32> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @test_unsigned_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i32_to_v2f64
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; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0
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; CHECK-NEXT: ucvtf.2d v0, [[VAL64]]
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; CHECK-NEXT: ret
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%conv = uitofp <2 x i32> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @test_signed_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i16_to_v2f64:
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; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16
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; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
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; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
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; CHECK: scvtf.2d v0, [[VAL64]]
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%conv = sitofp <2 x i16> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @test_unsigned_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i16_to_v2f64
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; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
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; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
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; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
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; CHECK: ucvtf.2d v0, [[VAL64]]
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%conv = uitofp <2 x i16> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @test_signed_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i8_to_v2f64:
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; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24
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; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
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; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
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; CHECK: scvtf.2d v0, [[VAL64]]
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%conv = sitofp <2 x i8> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x double> @test_unsigned_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i8_to_v2f64
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; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
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; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
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; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
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; CHECK: ucvtf.2d v0, [[VAL64]]
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%conv = uitofp <2 x i8> %v to <2 x double>
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ret <2 x double> %conv
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}
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define <2 x float> @test_signed_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i64_to_v2f32:
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; CHECK: scvtf.2d [[VAL64:v[0-9]+]], v0
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; CHECK: fcvtn v0.2s, [[VAL64]].2d
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%conv = sitofp <2 x i64> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <2 x float> @test_unsigned_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i64_to_v2f32
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; CHECK: ucvtf.2d [[VAL64:v[0-9]+]], v0
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; CHECK: fcvtn v0.2s, [[VAL64]].2d
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%conv = uitofp <2 x i64> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <2 x float> @test_signed_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i16_to_v2f32:
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; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16
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; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
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; CHECK: scvtf.2s v0, [[VAL32]]
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%conv = sitofp <2 x i16> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <2 x float> @test_unsigned_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i16_to_v2f32
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; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
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; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
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; CHECK: ucvtf.2s v0, [[VAL32]]
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%conv = uitofp <2 x i16> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <2 x float> @test_signed_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v2i8_to_v2f32:
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; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24
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; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
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; CHECK: scvtf.2s v0, [[VAL32]]
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%conv = sitofp <2 x i8> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <2 x float> @test_unsigned_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v2i8_to_v2f32
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; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
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; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
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; CHECK: ucvtf.2s v0, [[VAL32]]
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%conv = uitofp <2 x i8> %v to <2 x float>
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ret <2 x float> %conv
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}
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define <4 x float> @test_signed_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v4i16_to_v4f32:
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; CHECK: sshll.4s [[VAL32:v[0-9]+]], v0, #0
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; CHECK: scvtf.4s v0, [[VAL32]]
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%conv = sitofp <4 x i16> %v to <4 x float>
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ret <4 x float> %conv
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}
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define <4 x float> @test_unsigned_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v4i16_to_v4f32
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; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
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; CHECK: ucvtf.4s v0, [[VAL32]]
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%conv = uitofp <4 x i16> %v to <4 x float>
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ret <4 x float> %conv
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}
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define <4 x float> @test_signed_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_signed_v4i8_to_v4f32:
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; CHECK: shl.4h [[TMP:v[0-9]+]], v0, #8
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; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8
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; CHECK: sshll.4s [[VAL32:v[0-9]+]], [[VAL16]], #0
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; CHECK: scvtf.4s v0, [[VAL32]]
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%conv = sitofp <4 x i8> %v to <4 x float>
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ret <4 x float> %conv
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}
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define <4 x float> @test_unsigned_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
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; CHECK-LABEL: test_unsigned_v4i8_to_v4f32
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; CHECK: bic.4h v0, #0xff, lsl #8
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; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
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; CHECK: ucvtf.4s v0, [[VAL32]]
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%conv = uitofp <4 x i8> %v to <4 x float>
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ret <4 x float> %conv
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}
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