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Add capability to have a MachineBasicBlock as an operand to a MachineInstr
Add a bunch of methods to MachineOperand is* to reduce usage of MO_foo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5032 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -79,6 +79,7 @@ public:
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MO_SignExtendedImmed,
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MO_UnextendedImmed,
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MO_PCRelativeDisp,
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MO_MachineBasicBlock, // MachineBasicBlock reference
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};
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private:
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@ -98,23 +99,25 @@ private:
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// including hidden operands required for
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// the generated machine code.
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int64_t immedVal; // constant value for an explicit constant
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MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
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};
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MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
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char flags; // see bit field definitions above
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MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
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int regNum; // register number for an explicit register
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// will be set for a value after reg allocation
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private:
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MachineOperand()
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: immedVal(0),
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opType(MO_VirtualRegister),
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flags(0),
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opType(MO_VirtualRegister),
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regNum(-1) {}
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MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
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: immedVal(ImmVal),
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opType(OpTy),
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flags(0),
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opType(OpTy),
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regNum(-1) {}
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MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
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@ -139,11 +142,14 @@ private:
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}
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}
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MachineOperand(MachineBasicBlock *mbb)
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: MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
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public:
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MachineOperand(const MachineOperand &M)
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: immedVal(M.immedVal),
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opType(M.opType),
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flags(M.flags),
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opType(M.opType),
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regNum(M.regNum) {}
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~MachineOperand() {}
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@ -163,8 +169,17 @@ public:
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return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
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&& regNum >= MRegisterInfo::FirstVirtualRegister;
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}
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bool isPhysicalRegister() const {
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return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
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&& regNum < MRegisterInfo::FirstVirtualRegister;
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}
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bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
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bool isMachineRegister() const { return !isVirtualRegister(); }
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bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
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bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
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bool isImmediate() const {
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return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
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}
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inline Value* getVRegValue () const {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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@ -180,9 +195,14 @@ public:
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return regNum;
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}
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inline int64_t getImmedValue () const {
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assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
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assert(isImmediate());
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return immedVal;
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}
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MachineBasicBlock *getMachineBasicBlock() const {
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assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
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return MBB;
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}
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bool opIsDef () const { return flags & DEFFLAG; }
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bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
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bool opHiBits32 () const { return flags & HIFLAG32; }
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@ -482,6 +502,11 @@ public:
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MachineOperand::MO_SignExtendedImmed));
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}
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void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
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assert(!OperandsComplete() &&
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"Trying to add an operand to a machine instr that is already done!");
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operands.push_back(MachineOperand(MBB));
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}
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unsigned substituteValue(const Value* oldVal, Value* newVal,
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bool defsOnly = true);
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@ -81,6 +81,11 @@ struct MachineInstrBuilder {
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MI->addZeroExtImmOperand(Val);
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return *this;
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}
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const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB) const {
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MI->addMachineBasicBlockOperand(MBB);
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return *this;
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}
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};
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/// BuildMI - Builder interface. Specify how to create the initial instruction
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