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Add readcyclecounter lowering on PPC64.
On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -411,6 +411,9 @@ def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
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[SDNPHasChain, SDNPMayLoad, SDNPMayStore,
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SDNPMemOperand]>;
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def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
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[SDNPHasChain, SDNPSideEffect]>;
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def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier,
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[SDNPHasChain, SDNPSideEffect]>;
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@ -394,8 +394,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
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}
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if (Subtarget->has64BitSupport())
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if (Subtarget->has64BitSupport()) {
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setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
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setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
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}
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setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
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@ -265,6 +265,11 @@ def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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let Pattern = [(set G8RC:$rT, readcyclecounter)] in
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def MFTB8 : XFXForm_1_ext<31, 371, 268, (outs G8RC:$rT), (ins),
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"mftb $rT", SprMFTB>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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let Defs = [X1], Uses = [X1] in
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def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"",
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[(set G8RC:$result,
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15
test/CodeGen/PowerPC/ppc64-cyclecounter.ll
Normal file
15
test/CodeGen/PowerPC/ppc64-cyclecounter.ll
Normal file
@ -0,0 +1,15 @@
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; RUN: llc < %s | FileCheck %s
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define i64 @test1() nounwind {
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entry:
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%r = call i64 @llvm.readcyclecounter()
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ret i64 %r
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}
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; CHECK: @test1
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; CHECK: mftb
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declare i64 @llvm.readcyclecounter()
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