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Clear kill flags in InstrEmitter::EmitSubregNode().

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When a local virtual register is made global, make sure to clear any
existing kill flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159461 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-06-29 21:00:03 +00:00
parent bb0721680c
commit 8ccaad526a
2 changed files with 38 additions and 2 deletions
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1
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -470,6 +470,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
VRBase = MRI->createVirtualRegister(TRC);
BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
MRI->clearKillFlags(SrcReg);
} else {
// VReg may not support a SubIdx sub-register, and we may need to
// constrain its register class or issue a COPY to a compatible register

39
test/CodeGen/X86/crash.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -march=x86 %s -o -
; RUN: llc -march=x86-64 %s -o -
; RUN: llc -march=x86 < %s -verify-machineinstrs
; RUN: llc -march=x86-64 < %s -verify-machineinstrs
; PR6497
@ -391,3 +391,38 @@ if.end:
%t11 = tail call i64 asm sideeffect "foo", "=*m,=A,{bx},{cx},1,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %t6, i32 0, i32 0, i64 0) nounwind
ret void
}
; Avoid emitting wrong kill flags from InstrEmitter.
; InstrEmitter::EmitSubregNode() may steal virtual registers from already
; emitted blocks when isCoalescableExtInstr points out the opportunity.
; Make sure kill flags are cleared on the newly global virtual register.
define i64 @ov_read(i8* %vf, i8* nocapture %buffer, i32 %length, i32 %bigendianp, i32 %word, i32 %sgned, i32* %bitstream) nounwind uwtable ssp {
entry:
br i1 undef, label %return, label %while.body.preheader
while.body.preheader: ; preds = %entry
br i1 undef, label %if.then3, label %if.end7
if.then3: ; preds = %while.body.preheader
%0 = load i32* undef, align 4
br i1 undef, label %land.lhs.true.i255, label %if.end7
land.lhs.true.i255: ; preds = %if.then3
br i1 undef, label %if.then.i256, label %if.end7
if.then.i256: ; preds = %land.lhs.true.i255
%sub.i = sub i32 0, %0
%conv = sext i32 %sub.i to i64
br i1 undef, label %if.end7, label %while.end
if.end7: ; preds = %if.then.i256, %land.lhs.true.i255, %if.then3, %while.body.preheader
unreachable
while.end: ; preds = %if.then.i256
%cmp18 = icmp sgt i32 %sub.i, 0
%.conv = select i1 %cmp18, i64 -131, i64 %conv
ret i64 %.conv
return: ; preds = %entry
ret i64 -131
}