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Add some basic patterns for other datatypes

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27116 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-25 07:39:07 +00:00
parent 150ffa7842
commit 8d052bc711
2 changed files with 12 additions and 10 deletions
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6
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -172,7 +172,6 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
@ -181,14 +180,13 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
setOperationAction(ISD::ADD , MVT::v4f32, Legal);
setOperationAction(ISD::SUB , MVT::v4f32, Legal);
setOperationAction(ISD::MUL , MVT::v4f32, Legal);
setOperationAction(ISD::LOAD , MVT::v4f32, Legal);
setOperationAction(ISD::ADD , MVT::v4i32, Legal);
setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
setOperationAction(ISD::LOAD , MVT::v16i8, Legal);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);

16
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -513,10 +513,10 @@ def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
"lvebx $vD, $src", LdStGeneral,
[]>;
[(set VRRC:$vD, (v16i8 (PPClve_x xoaddr:$src)))]>;
def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
"lvehx $vD, $src", LdStGeneral,
[]>;
[(set VRRC:$vD, (v8i16 (PPClve_x xoaddr:$src)))]>;
def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
"lvewx $vD, $src", LdStGeneral,
[(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
@ -1244,10 +1244,9 @@ def : Pat<(f64 (extload iaddr:$src, f32)),
def : Pat<(f64 (extload xaddr:$src, f32)),
(FMRSD (LFSX xaddr:$src))>;
def : Pat<(v4i32 (load xoaddr:$src)),
(v4i32 (LVX xoaddr:$src))>;
def : Pat<(v16i8 (load xoaddr:$src)),
(v16i8 (LVX xoaddr:$src))>;
def : Pat<(v4i32 (load xoaddr:$src)), (v4i32 (LVX xoaddr:$src))>;
def : Pat<(v8i16 (load xoaddr:$src)), (v8i16 (LVX xoaddr:$src))>;
def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
@ -1256,8 +1255,13 @@ def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC),
(v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;
def : Pat<(store (v16i8 VRRC:$rS), xoaddr:$dst),
(STVX (v16i8 VRRC:$rS), xoaddr:$dst)>;
def : Pat<(store (v8i16 VRRC:$rS), xoaddr:$dst),
(STVX (v8i16 VRRC:$rS), xoaddr:$dst)>;
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
(v4i32 (LVEWX xoaddr:$src))>;