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[XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -100,6 +100,11 @@ static DecodeStatus Decode2RInstruction(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -344,6 +349,19 @@ Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S != MCDisassembler::Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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Inst.addOperand(MCOperand::CreateImm(Op1));
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus
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DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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@ -158,6 +158,14 @@ class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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let DecoderMethod = "Decode2RInstruction";
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}
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// 2R with first operand as an immediate. Used for TSETMR where the first
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// operand is treated as an immediate since it refers to a register number in
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// another thread.
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class _F2RImm<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: _F2R<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "Decode2RImmInstruction";
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}
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// 2R with first operand as both a source and a destination.
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class _F2RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern> : _F2R<opc, outs, ins, asmstr, pattern> {
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@ -700,7 +700,6 @@ def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]",
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}
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// Two operand short
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// TODO eet, eef, tsetmr
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def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
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"not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
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@ -848,6 +847,15 @@ def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
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"endin $dst, res[$src]",
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[(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
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def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b),
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"eef $a, res[$b]", []>;
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def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b),
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"eet $a, res[$b]", []>;
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def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b),
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"tsetmr r$a, $b", []>;
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// Two operand long
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def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
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"bitrev $dst, $src",
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@ -217,6 +217,15 @@
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# CHECK: sext r9, r1
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0x45 0x37
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# CHECK: tsetmr r7, r3
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0x1f 0x1f
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# CHECK: eef r1, res[r6]
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0x96 0x2f
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# CHECK: eet r11, res[r0]
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0x5c 0x27
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# rus instructions
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# CHECK: chkct res[r1], 8
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