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[XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -140,6 +140,11 @@ static DecodeStatus Decode3RInstruction(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -313,6 +318,9 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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case 0x16:
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Inst.setOpcode(XCore::EQ_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x17:
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Inst.setOpcode(XCore::TSETR_3r);
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return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
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case 0x18:
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Inst.setOpcode(XCore::LSS_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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@ -515,6 +523,19 @@ Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3;
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DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
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if (S == MCDisassembler::Success) {
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Inst.addOperand(MCOperand::CreateImm(Op1));
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
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}
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return S;
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}
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static DecodeStatus
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Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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@ -39,6 +39,14 @@ class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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let DecoderMethod = "Decode3RInstruction";
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}
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// 3R with first operand as an immediate. Used for TSETR where the first
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// operand is treated as an immediate since it refers to a register number in
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// another thread.
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class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: _F3R<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "Decode3RImmInstruction";
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}
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class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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let Inst{31-27} = opc{8-4};
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@ -395,7 +395,11 @@ def STW_2rus : _F2RUS<0b0000, (outs),
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defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
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defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
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// TODO tsetr
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// The first operand is treated as an immediate since it refers to a register
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// number in another thread.
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def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c),
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"set t[$c]:r$a, $b", []>;
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// Three operand long
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def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
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@ -325,6 +325,9 @@
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# CHECK: sub r4, r2, r5
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0x89 0x1a
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# CHECK: set t[r0]:r1, r2
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0x18 0xb8
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# 2rus instructions
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# CHECK: add r10, r2, 5
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