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Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62413 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-01-17 07:09:27 +00:00
parent 7ab2450674
commit 8e27826649
3 changed files with 32 additions and 15 deletions
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27
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@@ -817,7 +817,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
AM.IndexReg = ShVal.getNode()->getOperand(0);
ConstantSDNode *AddVal =
cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
uint64_t Disp = AM.Disp + (AddVal->getZExtValue() << Val);
uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
if (!is64Bit || isInt32(Disp))
AM.Disp = Disp;
else
@@ -858,7 +858,7 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
Reg = MulVal.getNode()->getOperand(0);
ConstantSDNode *AddVal =
cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
uint64_t Disp = AM.Disp + AddVal->getZExtValue() *
uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
CN->getZExtValue();
if (!is64Bit || isInt32(Disp))
AM.Disp = Disp;
@@ -874,19 +874,18 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
}
break;
case ISD::ADD:
{
X86ISelAddressMode Backup = AM;
if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1) &&
!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1))
return false;
AM = Backup;
if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1) &&
!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1))
return false;
AM = Backup;
}
case ISD::ADD: {
X86ISelAddressMode Backup = AM;
if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1) &&
!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1))
return false;
AM = Backup;
if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1) &&
!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1))
return false;
AM = Backup;
break;
}
case ISD::OR:
// Handle "X | C" as "X + C" iff X is known to have C bits clear.

1
test/CodeGen/X86/lea-3.ll
View File

@@ -1,4 +1,3 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep {leal (%rdi,%rdi,2), %eax}
define i32 @test(i32 %a) {
%tmp2 = mul i32 %a, 3 ; <i32> [#uses=1]

19
test/CodeGen/X86/lea-4.ll Normal file
View File

@@ -0,0 +1,19 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep lea | count 2
define zeroext i16 @t1(i32 %on_off) nounwind {
entry:
%0 = sub i32 %on_off, 1
%1 = mul i32 %0, 2
%2 = trunc i32 %1 to i16
%3 = zext i16 %2 to i32
%4 = trunc i32 %3 to i16
ret i16 %4
}
define i32 @t2(i32 %on_off) nounwind {
entry:
%0 = sub i32 %on_off, 1
%1 = mul i32 %0, 2
%2 = and i32 %1, 65535
ret i32 %2
}