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Fix a problem where constant expr shifts would not have their shift amount

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promoted to the right type.  This fixes: IA64/2005-08-22-LegalizerCrash.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22969 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-22 17:28:31 +00:00
parent 4c23c5b330
commit 8f03405ee5
1 changed files with 5 additions and 5 deletions
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10
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -337,7 +337,7 @@ public:
void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
//
void visitBinary(User &I, unsigned Opcode);
void visitBinary(User &I, unsigned Opcode, bool isShift = false);
void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
void visitSub(User &I);
void visitMul(User &I) { visitBinary(I, ISD::MUL); }
@ -350,9 +350,9 @@ public:
void visitAnd(User &I) { visitBinary(I, ISD::AND); }
void visitOr (User &I) { visitBinary(I, ISD::OR); }
void visitXor(User &I) { visitBinary(I, ISD::XOR); }
void visitShl(User &I) { visitBinary(I, ISD::SHL); }
void visitShl(User &I) { visitBinary(I, ISD::SHL, true); }
void visitShr(User &I) {
visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA, true);
}
void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
@ -486,11 +486,11 @@ void SelectionDAGLowering::visitSub(User &I) {
visitBinary(I, ISD::SUB);
}
void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode) {
void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode, bool isShift) {
SDOperand Op1 = getValue(I.getOperand(0));
SDOperand Op2 = getValue(I.getOperand(1));
if (isa<ShiftInst>(I))
if (isShift)
Op2 = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), Op2);
setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));