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https://github.com/c64scene-ar/llvm-6502.git
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More support for machine code emission: raw instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4872 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -13,10 +13,12 @@
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namespace {
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struct Emitter : public FunctionPass {
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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X86TargetMachine &TM;
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const X86InstrInfo ⅈ
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MachineCodeEmitter &MCE;
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Emitter(TargetMachine &tm, MachineCodeEmitter &mce) : TM(tm), MCE(mce) {}
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Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
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: TM(tm), II(TM.getInstrInfo()), MCE(mce) {}
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bool runOnFunction(Function &F);
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@ -56,14 +58,21 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) {
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void Emitter::emitInstruction(MachineInstr &MI) {
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unsigned Opcode = MI.getOpcode();
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const MachineInstrDescriptor &Desc = TM.getInstrInfo().get(Opcode);
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const MachineInstrDescriptor &Desc = II.get(Opcode);
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// Emit instruction prefixes if neccesary
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if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
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if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F); // Two-byte opcode prefix
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if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::RawFrm:
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;
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MCE.emitByte(II.getBaseOpcodeFor(Opcode));
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if (MI.getNumOperands() == 1) {
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assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp);
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MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue());
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}
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break;
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}
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}
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@ -13,10 +13,12 @@
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namespace {
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struct Emitter : public FunctionPass {
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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X86TargetMachine &TM;
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const X86InstrInfo ⅈ
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MachineCodeEmitter &MCE;
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Emitter(TargetMachine &tm, MachineCodeEmitter &mce) : TM(tm), MCE(mce) {}
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Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
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: TM(tm), II(TM.getInstrInfo()), MCE(mce) {}
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bool runOnFunction(Function &F);
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@ -56,14 +58,21 @@ void Emitter::emitBasicBlock(MachineBasicBlock &MBB) {
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void Emitter::emitInstruction(MachineInstr &MI) {
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unsigned Opcode = MI.getOpcode();
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const MachineInstrDescriptor &Desc = TM.getInstrInfo().get(Opcode);
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const MachineInstrDescriptor &Desc = II.get(Opcode);
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// Emit instruction prefixes if neccesary
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if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
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if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F); // Two-byte opcode prefix
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if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::RawFrm:
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;
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MCE.emitByte(II.getBaseOpcodeFor(Opcode));
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if (MI.getNumOperands() == 1) {
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assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp);
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MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue());
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}
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break;
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}
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}
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