mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Remove support for 64b PPC, it's been broken for a long time. It'll be
back once a DAG->DAG ISel exists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22778 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
7ac17529d2
commit
8f331325a2
@ -8,12 +8,11 @@
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = LLVMPowerPC
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TARGET = PowerPC PPC32 PPC64
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TARGET = PowerPC PPC32
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
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PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
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PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \
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PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc
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PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc
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include $(LEVEL)/Makefile.common
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@ -1,35 +0,0 @@
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//===-- PPC64CodeEmitter.cpp - JIT Code Emitter for PPC64 -----*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "PPC64JITInfo.h"
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#include "PPC64TargetMachine.h"
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using namespace llvm;
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
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/// machine code emitted. This uses a MachineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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bool PPC64TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
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MachineCodeEmitter &MCE) {
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return true;
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// It should go something like this:
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// PM.add(new Emitter(MCE)); // Machine code emitter pass for PPC64
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// Delete machine code for this function after emitting it:
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// PM.add(createMachineCodeDeleter());
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}
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void PPC64JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
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assert (0 && "PPC64JITInfo::replaceMachineCodeForFunction not implemented");
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}
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File diff suppressed because it is too large
Load Diff
@ -1,59 +0,0 @@
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//===- PPC64InstrInfo.cpp - PowerPC64 Instruction Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPC.h"
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#include "PPC64InstrInfo.h"
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#include "PPC64GenInstrInfo.inc"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include <iostream>
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using namespace llvm;
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PPC64InstrInfo::PPC64InstrInfo()
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: TargetInstrInfo(PPC64Insts, sizeof(PPC64Insts)/sizeof(PPC64Insts[0])) { }
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bool PPC64InstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == PPC::OR) { // or r1, r2, r2
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isRegister() &&
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"invalid PPC OR instruction!");
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if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::ADDI) { // addi r1, r2, 0
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(2).isImmediate() &&
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"invalid PPC ADDI instruction!");
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if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::FMR) { // fmr r1, r2
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid PPC FMR instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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@ -1,56 +0,0 @@
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//===- PPC64InstrInfo.h - PowerPC64 Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPC64_INSTRUCTIONINFO_H
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#define POWERPC64_INSTRUCTIONINFO_H
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#include "PowerPCInstrInfo.h"
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#include "PPC64RegisterInfo.h"
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namespace llvm {
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class PPC64InstrInfo : public TargetInstrInfo {
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const PPC64RegisterInfo RI;
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public:
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PPC64InstrInfo();
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
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//
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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//
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const;
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static unsigned invertPPCBranchOpcode(unsigned Opcode) {
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switch (Opcode) {
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default: assert(0 && "Unknown PPC branch opcode!");
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case PPC::BEQ: return PPC::BNE;
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case PPC::BNE: return PPC::BEQ;
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case PPC::BLT: return PPC::BGE;
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case PPC::BGE: return PPC::BLT;
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case PPC::BGT: return PPC::BLE;
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case PPC::BLE: return PPC::BGT;
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}
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}
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};
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}
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#endif
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@ -1,35 +0,0 @@
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//===- PPC64JITInfo.h - PowerPC/AIX impl. of the JIT interface -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC/AIX implementation of the TargetJITInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPC_AIX_JITINFO_H
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#define POWERPC_AIX_JITINFO_H
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#include "PowerPCJITInfo.h"
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namespace llvm {
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class TargetMachine;
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class PPC64JITInfo : public PowerPCJITInfo {
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public:
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PPC64JITInfo(TargetMachine &tm) : PowerPCJITInfo(tm) {}
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/// replaceMachineCodeForFunction - Make it so that calling the function
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/// whose machine code is at OLD turns into a call to NEW, perhaps by
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/// overwriting OLD with a branch to NEW. This is used for self-modifying
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/// code.
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///
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virtual void replaceMachineCodeForFunction(void *Old, void *New);
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};
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}
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#endif
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@ -1,317 +0,0 @@
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//===- PPC64RegisterInfo.cpp - PowerPC64 Register Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC64 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "PowerPC.h"
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#include "PowerPCInstrBuilder.h"
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#include "PPC64RegisterInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/STLExtras.h"
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#include <cstdlib>
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#include <iostream>
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using namespace llvm;
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PPC64RegisterInfo::PPC64RegisterInfo()
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: PPC64GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
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ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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ImmToIdxMap[PPC::ADDI] = PPC::ADD;
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}
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static const TargetRegisterClass *getClass(unsigned SrcReg) {
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if (PPC64::FPRCRegisterClass->contains(SrcReg))
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return PPC64::FPRCRegisterClass;
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assert(PPC64::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
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return PPC64::GPRCRegisterClass;
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}
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static unsigned getIdx(const TargetRegisterClass *RC) {
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if (RC == PPC64::GPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 1: return 0;
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case 2: return 1;
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case 4: return 2;
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case 8: return 3;
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}
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} else if (RC == PPC64::FPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 4: return 4;
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case 8: return 5;
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}
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}
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std::cerr << "Invalid register class to getIdx()!\n";
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abort();
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}
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void
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PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx) const {
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static const unsigned Opcode[] = {
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PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
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};
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unsigned OC = Opcode[getIdx(getClass(SrcReg))];
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if (SrcReg == PPC::LR) {
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BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
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BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
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addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
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} else {
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BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
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addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
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}
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}
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void
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PPC64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx) const{
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static const unsigned Opcode[] = {
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PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
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};
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unsigned OC = Opcode[getIdx(getClass(DestReg))];
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if (DestReg == PPC::LR) {
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BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
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addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
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BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
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} else {
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BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
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addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
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}
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}
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void PPC64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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MachineInstr *I;
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if (RC == PPC64::GPRCRegisterClass) {
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BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == PPC64::FPRCRegisterClass) {
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BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
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} else {
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std::cerr << "Attempt to copy register that is not GPR or FPR";
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abort();
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}
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(MachineFunction &MF) {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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return MFI->hasVarSizedObjects();
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}
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void PPC64RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (hasFP(MF)) {
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// If we have a frame pointer, convert as follows:
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// ADJCALLSTACKDOWN -> addi, r1, r1, -amount
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// ADJCALLSTACKUP -> addi, r1, r1, amount
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MachineInstr *Old = I;
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unsigned Amount = Old->getOperand(0).getImmedValue();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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// Replace the pseudo instruction with a new instruction...
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if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
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MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
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.addSImm(-Amount));
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} else {
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assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
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MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
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.addSImm(Amount));
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}
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}
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}
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MBB.erase(I);
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}
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void
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PPC64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
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MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
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// Take into account whether it's an add or mem instruction
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unsigned OffIdx = (i == 2) ? 1 : 2;
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// Now add the frame object offset to the offset from r1.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(OffIdx).getImmedValue();
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// If we're not using a Frame Pointer that has been set to the value of the
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// SP before having the stack size subtracted from it, then add the stack size
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// to Offset to get the correct offset.
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Offset += MF.getFrameInfo()->getStackSize();
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if (Offset > 32767 || Offset < -32768) {
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// Insert a set of r0 with the full offset value before the ld, st, or add
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MachineBasicBlock *MBB = MI.getParent();
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MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
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MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
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.addImm(Offset));
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// convert into indexed form of the instruction
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// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
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// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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unsigned NewOpcode =
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const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
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assert(NewOpcode && "No indexed form of load or store available!");
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MI.setOpcode(NewOpcode);
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MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
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MI.SetMachineOperandReg(2, PPC::R0);
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} else {
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||||
MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
|
||||
Offset);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void PPC64RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
MachineInstr *MI;
|
||||
|
||||
// Get the number of bytes to allocate from the FrameInfo
|
||||
unsigned NumBytes = MFI->getStackSize();
|
||||
|
||||
// If we have calls, we cannot use the red zone to store callee save registers
|
||||
// and we must set up a stack frame, so calculate the necessary size here.
|
||||
if (MFI->hasCalls()) {
|
||||
// We reserve argument space for call sites in the function immediately on
|
||||
// entry to the current function. This eliminates the need for add/sub
|
||||
// brackets around call sites.
|
||||
NumBytes += MFI->getMaxCallFrameSize();
|
||||
}
|
||||
|
||||
// Do we need to allocate space on the stack?
|
||||
if (NumBytes == 0) return;
|
||||
|
||||
// Add the size of R1 to NumBytes size for the store of R1 to the bottom
|
||||
// of the stack and round the size to a multiple of the alignment.
|
||||
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
|
||||
unsigned GPRSize = getSpillSize(PPC::R1)/8;
|
||||
unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
|
||||
NumBytes = (NumBytes+Size+Align-1)/Align*Align;
|
||||
|
||||
// Update frame info to pretend that this is part of the stack...
|
||||
MFI->setStackSize(NumBytes);
|
||||
|
||||
// adjust stack pointer: r1 -= numbytes
|
||||
if (NumBytes <= 32768) {
|
||||
MI=BuildMI(PPC::STDU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
|
||||
MBB.insert(MBBI, MI);
|
||||
} else {
|
||||
int NegNumbytes = -NumBytes;
|
||||
MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
|
||||
MBB.insert(MBBI, MI);
|
||||
MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
|
||||
.addImm(NegNumbytes & 0xFFFF);
|
||||
MBB.insert(MBBI, MI);
|
||||
MI = BuildMI(PPC::STDUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
|
||||
MBB.insert(MBBI, MI);
|
||||
}
|
||||
|
||||
if (hasFP(MF)) {
|
||||
MI = BuildMI(PPC::STD, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
|
||||
MBB.insert(MBBI, MI);
|
||||
MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
|
||||
MBB.insert(MBBI, MI);
|
||||
}
|
||||
}
|
||||
|
||||
void PPC64RegisterInfo::emitEpilogue(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) const {
|
||||
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
||||
MachineInstr *MI;
|
||||
assert(MBBI->getOpcode() == PPC::BLR &&
|
||||
"Can only insert epilog into returning blocks");
|
||||
|
||||
// Get the number of bytes allocated from the FrameInfo...
|
||||
unsigned NumBytes = MFI->getStackSize();
|
||||
|
||||
if (NumBytes != 0) {
|
||||
if (hasFP(MF)) {
|
||||
MI = BuildMI(PPC::OR, 2, PPC::R1).addReg(PPC::R31).addReg(PPC::R31);
|
||||
MBB.insert(MBBI, MI);
|
||||
MI = BuildMI(PPC::LD, 2, PPC::R31).addSImm(4).addReg(PPC::R31);
|
||||
MBB.insert(MBBI, MI);
|
||||
}
|
||||
MI = BuildMI(PPC::LD, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
|
||||
MBB.insert(MBBI, MI);
|
||||
}
|
||||
}
|
||||
|
||||
#include "PPC64GenRegisterInfo.inc"
|
||||
|
||||
const TargetRegisterClass*
|
||||
PPC64RegisterInfo::getRegClassForType(const Type* Ty) const {
|
||||
switch (Ty->getTypeID()) {
|
||||
default: assert(0 && "Invalid type to getClass!");
|
||||
case Type::BoolTyID:
|
||||
case Type::SByteTyID:
|
||||
case Type::UByteTyID:
|
||||
case Type::ShortTyID:
|
||||
case Type::UShortTyID:
|
||||
case Type::IntTyID:
|
||||
case Type::UIntTyID:
|
||||
case Type::PointerTyID:
|
||||
case Type::LongTyID:
|
||||
case Type::ULongTyID: return &GPRCInstance;
|
||||
|
||||
case Type::FloatTyID:
|
||||
case Type::DoubleTyID: return &FPRCInstance;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,56 +0,0 @@
|
||||
//===- PPC64RegisterInfo.h - PowerPC64 Register Information Impl -*- C++ -*-==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the PowerPC implementation of the MRegisterInfo class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef POWERPC64_REGISTERINFO_H
|
||||
#define POWERPC64_REGISTERINFO_H
|
||||
|
||||
#include "PowerPC.h"
|
||||
#include "PPC64GenRegisterInfo.h.inc"
|
||||
#include <map>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class Type;
|
||||
|
||||
class PPC64RegisterInfo : public PPC64GenRegisterInfo {
|
||||
std::map<unsigned, unsigned> ImmToIdxMap;
|
||||
public:
|
||||
PPC64RegisterInfo();
|
||||
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
|
||||
|
||||
/// Code Generation virtual methods...
|
||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned SrcReg, int FrameIndex) const;
|
||||
|
||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, int FrameIndex) const;
|
||||
|
||||
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I) const;
|
||||
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
|
||||
|
||||
void emitPrologue(MachineFunction &MF) const;
|
||||
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
@ -1,43 +0,0 @@
|
||||
//===-- PPC64TargetMachine.h - Define TargetMachine for PowerPC64 -*- C++ -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file declares the PowerPC specific subclass of TargetMachine.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef POWERPC64_TARGETMACHINE_H
|
||||
#define POWERPC64_TARGETMACHINE_H
|
||||
|
||||
#include "PowerPCTargetMachine.h"
|
||||
#include "PPC64InstrInfo.h"
|
||||
#include "llvm/PassManager.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class IntrinsicLowering;
|
||||
|
||||
class PPC64TargetMachine : public PowerPCTargetMachine {
|
||||
PPC64InstrInfo InstrInfo;
|
||||
|
||||
public:
|
||||
PPC64TargetMachine(const Module &M, IntrinsicLowering *IL);
|
||||
virtual const PPC64InstrInfo *getInstrInfo() const { return &InstrInfo; }
|
||||
virtual const MRegisterInfo *getRegisterInfo() const {
|
||||
return &InstrInfo.getRegisterInfo();
|
||||
}
|
||||
|
||||
static unsigned getModuleMatchQuality(const Module &M);
|
||||
|
||||
bool addPassesToEmitMachineCode(FunctionPassManager &PM,
|
||||
MachineCodeEmitter &MCE);
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
@ -14,9 +14,7 @@
|
||||
#include "PowerPCTargetMachine.h"
|
||||
#include "PowerPCFrameInfo.h"
|
||||
#include "PPC32TargetMachine.h"
|
||||
#include "PPC64TargetMachine.h"
|
||||
#include "PPC32JITInfo.h"
|
||||
#include "PPC64JITInfo.h"
|
||||
#include "llvm/Module.h"
|
||||
#include "llvm/PassManager.h"
|
||||
#include "llvm/Analysis/Verifier.h"
|
||||
@ -35,16 +33,10 @@ static cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc", cl::Hidden,
|
||||
|
||||
namespace {
|
||||
const std::string PPC32ID = "PowerPC/32bit";
|
||||
const std::string PPC64ID = "PowerPC/64bit";
|
||||
|
||||
// Register the targets
|
||||
RegisterTarget<PPC32TargetMachine>
|
||||
X("ppc32", " PowerPC 32-bit");
|
||||
|
||||
#if 0
|
||||
RegisterTarget<PPC64TargetMachine>
|
||||
Y("ppc64", " PowerPC 64-bit (unimplemented)");
|
||||
#endif
|
||||
}
|
||||
|
||||
PowerPCTargetMachine::PowerPCTargetMachine(const std::string &name,
|
||||
@ -75,8 +67,6 @@ bool PowerPCTargetMachine::addPassesToEmitFile(PassManager &PM,
|
||||
CodeGenFileType FileType) {
|
||||
if (FileType != TargetMachine::AssemblyFile) return true;
|
||||
|
||||
bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(this));
|
||||
|
||||
if (EnablePPCLSR) {
|
||||
PM.add(createLoopStrengthReducePass());
|
||||
PM.add(createVerifierPass());
|
||||
@ -98,9 +88,7 @@ bool PowerPCTargetMachine::addPassesToEmitFile(PassManager &PM,
|
||||
PM.add(createUnreachableBlockEliminationPass());
|
||||
|
||||
// Default to pattern ISel
|
||||
if (LP64)
|
||||
PM.add(createPPC64ISelPattern(*this));
|
||||
else if (PatternISelTriState == 0)
|
||||
if (PatternISelTriState == 0)
|
||||
PM.add(createPPC32ISelSimple(*this));
|
||||
else
|
||||
PM.add(createPPC32ISelPattern(*this));
|
||||
@ -138,8 +126,6 @@ void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
|
||||
// The JIT does not support or need PIC.
|
||||
PICEnabled = false;
|
||||
|
||||
bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(&TM));
|
||||
|
||||
if (EnablePPCLSR) {
|
||||
PM.add(createLoopStrengthReducePass());
|
||||
PM.add(createCFGSimplificationPass());
|
||||
@ -160,9 +146,7 @@ void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
|
||||
PM.add(createUnreachableBlockEliminationPass());
|
||||
|
||||
// Default to pattern ISel
|
||||
if (LP64)
|
||||
PM.add(createPPC64ISelPattern(TM));
|
||||
else if (PatternISelTriState == 0)
|
||||
if (PatternISelTriState == 0)
|
||||
PM.add(createPPC32ISelSimple(TM));
|
||||
else
|
||||
PM.add(createPPC32ISelPattern(TM));
|
||||
@ -184,13 +168,6 @@ PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL)
|
||||
TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
|
||||
PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
|
||||
|
||||
/// PPC64TargetMachine ctor - Create a LP64 architecture model
|
||||
///
|
||||
PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL)
|
||||
: PowerPCTargetMachine(PPC64ID, IL, M,
|
||||
TargetData(PPC64ID,false,8,4,4,4,4,4,2,1,1),
|
||||
PowerPCFrameInfo(*this, true)) {}
|
||||
|
||||
unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
|
||||
// We strongly match "powerpc-*".
|
||||
std::string TT = M.getTargetTriple();
|
||||
@ -206,14 +183,3 @@ unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
|
||||
|
||||
return getJITMatchQuality()/2;
|
||||
}
|
||||
|
||||
unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
|
||||
if (M.getEndianness() == Module::BigEndian &&
|
||||
M.getPointerSize() == Module::Pointer64)
|
||||
return 10; // Direct match
|
||||
else if (M.getEndianness() != Module::AnyEndianness ||
|
||||
M.getPointerSize() != Module::AnyPointerSize)
|
||||
return 0; // Match for some other target
|
||||
|
||||
return getJITMatchQuality()/2;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user