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Factor a bunch of the rules and add support for generating the asmwriter.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15388 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-08-01 06:01:32 +00:00
parent 96563df090
commit 8f945d7756
1 changed files with 23 additions and 21 deletions
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44
lib/Target/X86/Makefile
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@ -10,42 +10,44 @@ LEVEL = ../../..
LIBRARYNAME = x86
include $(LEVEL)/Makefile.common
TARGET = X86
# Make sure that tblgen is run, first thing.
$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
X86GenRegisterInfo.inc X86GenInstrNames.inc \
X86GenInstrInfo.inc X86GenInstrSelector.inc
X86GenInstrInfo.inc X86GenAsmWriter.inc \
X86GenInstrSelector.inc
X86GenRegisterNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
@echo "Building X86.td register names with tblgen"
TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
$(SourceDir)/../Target.td
$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td register names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
X86GenRegisterInfo.h.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
@echo "Building X86.td register information header with tblgen"
$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td register information header with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
X86GenRegisterInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
@echo "Building X86.td register information implementation with tblgen"
$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td register info implementation with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
X86GenInstrNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
@echo "Building X86.td instruction names with tblgen"
$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td instruction names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
X86GenInstrInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
@echo "Building X86.td instruction information with tblgen"
$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
X86GenInstrSelector.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
$(SourceDir)/../Target.td $(TBLGEN)
@echo "Building X86.td instruction selector with tblgen"
$(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td assembly writer with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@
$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td instruction selector with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
clean::
$(VERB) rm -f *.inc