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Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.

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Note that these are distinct from TargetInstrInfo::INSERT_SUBREG
and TargetInstrInfo::EXTRACT_SUBREG, which are used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68355 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-04-03 00:25:26 +00:00
parent 25f0ee5191
commit 8f9643f0f7
5 changed files with 0 additions and 58 deletions
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12
include/llvm/CodeGen/SelectionDAGNodes.h
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@ -327,18 +327,6 @@ namespace ISD {
/// elements 1 to N-1 of the N-element vector are undefined.
SCALAR_TO_VECTOR,
// EXTRACT_SUBREG - This node is used to extract a sub-register value.
// This node takes a superreg and a constant sub-register index as operands.
// Note sub-register indices must be increasing. That is, if the
// sub-register index of a 8-bit sub-register is N, then the index for a
// 16-bit sub-register must be at least N+1.
EXTRACT_SUBREG,
// INSERT_SUBREG - This node is used to insert a sub-register value.
// This node takes a superreg, a subreg value, and a constant sub-register
// index as operands.
INSERT_SUBREG,
// MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing
// an unsigned/signed value of type i[2*N], then return the top part.
MULHU, MULHS,

5
include/llvm/Target/TargetSelectionDAG.td
View File

@ -406,11 +406,6 @@ def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
SDTypeProfile<1, 2, []>>;
def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
SDTypeProfile<1, 3, []>>;
// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
// these internally. Don't reference these directly.
def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",

17
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -1589,23 +1589,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
AddLegalizedOperand(SDValue(Node, i), Tmp1);
}
return Tmp2;
case ISD::EXTRACT_SUBREG: {
Tmp1 = LegalizeOp(Node->getOperand(0));
ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
assert(idx && "Operand must be a constant");
Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
}
break;
case ISD::INSERT_SUBREG: {
Tmp1 = LegalizeOp(Node->getOperand(0));
Tmp2 = LegalizeOp(Node->getOperand(1));
ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
assert(idx && "Operand must be a constant");
Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
}
break;
case ISD::BUILD_VECTOR:
switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
default: assert(0 && "This action is not supported yet!");

3
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -5165,9 +5165,6 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::SRA_PARTS: return "sra_parts";
case ISD::SRL_PARTS: return "srl_parts";
case ISD::EXTRACT_SUBREG: return "extract_subreg";
case ISD::INSERT_SUBREG: return "insert_subreg";
// Conversion operators.
case ISD::SIGN_EXTEND: return "sign_extend";
case ISD::ZERO_EXTEND: return "zero_extend";

21
utils/TableGen/DAGISelEmitter.cpp
View File

@ -1967,25 +1967,6 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " MVT::Other, Tmp1, Tmp2, Chain);\n"
<< "}\n\n";
OS << "SDNode *Select_EXTRACT_SUBREG(const SDValue &N) {\n"
<< " SDValue N0 = N.getOperand(0);\n"
<< " SDValue N1 = N.getOperand(1);\n"
<< " unsigned C = cast<ConstantSDNode>(N1)->getZExtValue();\n"
<< " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::EXTRACT_SUBREG,\n"
<< " N.getValueType(), N0, Tmp);\n"
<< "}\n\n";
OS << "SDNode *Select_INSERT_SUBREG(const SDValue &N) {\n"
<< " SDValue N0 = N.getOperand(0);\n"
<< " SDValue N1 = N.getOperand(1);\n"
<< " SDValue N2 = N.getOperand(2);\n"
<< " unsigned C = cast<ConstantSDNode>(N2)->getZExtValue();\n"
<< " SDValue Tmp = CurDAG->getTargetConstant(C, MVT::i32);\n"
<< " return CurDAG->SelectNodeTo(N.getNode(), TargetInstrInfo::INSERT_SUBREG,\n"
<< " N.getValueType(), N0, N1, Tmp);\n"
<< "}\n\n";
OS << "// The main instruction selector code.\n"
<< "SDNode *SelectCode(SDValue N) {\n"
<< " MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT();\n"
@ -2020,8 +2001,6 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
<< " case ISD::DBG_LABEL: return Select_DBG_LABEL(N);\n"
<< " case ISD::EH_LABEL: return Select_EH_LABEL(N);\n"
<< " case ISD::DECLARE: return Select_DECLARE(N);\n"
<< " case ISD::EXTRACT_SUBREG: return Select_EXTRACT_SUBREG(N);\n"
<< " case ISD::INSERT_SUBREG: return Select_INSERT_SUBREG(N);\n"
<< " case ISD::UNDEF: return Select_UNDEF(N);\n";
// Loop over all of the case statements, emiting a call to each method we