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80 column and trailing whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103806 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
5468e0928b
commit
9001303a3f
@ -120,7 +120,7 @@ namespace {
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/// AvailableQueue - The priority queue to use for the available SUnits.
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///
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LatencyPriorityQueue AvailableQueue;
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/// PendingQueue - This contains all of the instructions whose operands have
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/// been issued, but their results are not ready yet (due to the latency of
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/// the operation). Once the operands becomes available, the instruction is
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@ -164,7 +164,7 @@ namespace {
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/// Schedule - Schedule the instruction range using list scheduling.
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///
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void Schedule();
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/// Observe - Update liveness information to account for the current
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/// instruction, which will not be scheduled.
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///
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@ -185,7 +185,7 @@ namespace {
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void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
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void ListScheduleTopDown();
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void StartBlockForKills(MachineBasicBlock *BB);
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// ToggleKillFlag - Toggle a register operand kill flag. Other
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// adjustments may be made to the instruction if necessary. Return
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// true if the operand has been deleted, false if not.
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@ -233,9 +233,10 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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// Check for antidep breaking override...
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if (EnableAntiDepBreaking.getPosition() > 0) {
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AntiDepMode = (EnableAntiDepBreaking == "all") ? TargetSubtarget::ANTIDEP_ALL :
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(EnableAntiDepBreaking == "critical") ? TargetSubtarget::ANTIDEP_CRITICAL :
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TargetSubtarget::ANTIDEP_NONE;
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AntiDepMode = (EnableAntiDepBreaking == "all") ?
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TargetSubtarget::ANTIDEP_ALL :
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(EnableAntiDepBreaking == "critical")
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? TargetSubtarget::ANTIDEP_CRITICAL : TargetSubtarget::ANTIDEP_NONE;
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}
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DEBUG(dbgs() << "PostRAScheduler\n");
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@ -246,10 +247,10 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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ScheduleHazardRecognizer *HR = EnablePostRAHazardAvoidance ?
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(ScheduleHazardRecognizer *)new ExactHazardRecognizer(InstrItins) :
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(ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
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AntiDepBreaker *ADB =
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AntiDepBreaker *ADB =
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((AntiDepMode == TargetSubtarget::ANTIDEP_ALL) ?
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(AntiDepBreaker *)new AggressiveAntiDepBreaker(Fn, CriticalPathRCs) :
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((AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ?
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((AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ?
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(AntiDepBreaker *)new CriticalAntiDepBreaker(Fn) : NULL));
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SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR, ADB, AA);
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@ -319,7 +320,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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return true;
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}
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/// StartBlock - Initialize register live-range state for scheduling in
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/// this block.
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///
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@ -340,10 +341,10 @@ void SchedulePostRATDList::Schedule() {
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BuildSchedGraph(AA);
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if (AntiDepBreak != NULL) {
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unsigned Broken =
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unsigned Broken =
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AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos,
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InsertPosIndex);
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if (Broken != 0) {
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// We made changes. Update the dependency graph.
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// Theoretically we could update the graph in place:
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@ -356,7 +357,7 @@ void SchedulePostRATDList::Schedule() {
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EntrySU = SUnit();
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ExitSU = SUnit();
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BuildSchedGraph(AA);
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NumFixedAnti += Broken;
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}
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}
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@ -434,7 +435,7 @@ bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
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MO.setIsKill(true);
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return false;
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}
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// If MO itself is live, clear the kill flag...
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if (KillIndices[MO.getReg()] != ~0u) {
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MO.setIsKill(false);
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@ -473,7 +474,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
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BitVector ReservedRegs = TRI->getReservedRegs(MF);
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StartBlockForKills(MBB);
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// Examine block from end to start...
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unsigned Count = MBB->size();
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for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
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@ -493,9 +494,9 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
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if (!MO.isDef()) continue;
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// Ignore two-addr defs.
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if (MI->isRegTiedToUseOperand(i)) continue;
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KillIndices[Reg] = ~0u;
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// Repeat for all subregs.
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg) {
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@ -530,17 +531,17 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
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if (kill)
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kill = (KillIndices[Reg] == ~0u);
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}
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if (MO.isKill() != kill) {
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DEBUG(dbgs() << "Fixing " << MO << " in ");
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// Warning: ToggleKillFlag may invalidate MO.
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ToggleKillFlag(MI, MO);
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DEBUG(MI->dump());
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}
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killedRegs.insert(Reg);
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}
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// Mark any used register (that is not using undef) and subregs as
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// now live...
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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@ -550,7 +551,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
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if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
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KillIndices[Reg] = Count;
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg) {
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KillIndices[*Subreg] = Count;
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@ -582,7 +583,7 @@ void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
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// available. This is the max of the start time of all predecessors plus
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// their latencies.
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SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
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// If all the node's predecessors are scheduled, this node is ready
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// to be scheduled. Ignore the special ExitSU node.
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if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
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@ -603,9 +604,9 @@ void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
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void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
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DEBUG(SU->dump(this));
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Sequence.push_back(SU);
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assert(CurCycle >= SU->getDepth() &&
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assert(CurCycle >= SU->getDepth() &&
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"Node scheduled above its depth!");
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SU->setDepthToAtLeast(CurCycle);
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@ -618,7 +619,7 @@ void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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/// schedulers.
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void SchedulePostRATDList::ListScheduleTopDown() {
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unsigned CurCycle = 0;
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// We're scheduling top-down but we're visiting the regions in
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// bottom-up order, so we don't know the hazards at the start of a
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// region. So assume no hazards (this should usually be ok as most
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