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T2 Load/Store Multiple:
These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1140,7 +1140,7 @@ static bool DisassembleThumb2LdStMul(MCInst &MI, unsigned Opcode, uint32_t insn,
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Opcode == ARM::t2STMIA || Opcode == ARM::t2STMIA_UPD ||
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Opcode == ARM::t2STMDB || Opcode == ARM::t2STMDB_UPD)
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&& "Unexpected opcode");
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assert(NumOps >= 5 && "Thumb2 LdStMul expects NumOps >= 5");
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assert(NumOps >= 4 && "Thumb2 LdStMul expects NumOps >= 4");
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NumOpsAdded = 0;
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