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https://github.com/c64scene-ar/llvm-6502.git
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[PowerPC] Remove need for adjustFixupOffst hack
Now that applyFixup understands differently-sized fixups, we can define fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte fixups, applied at an offset of 2 relative to the start of the instruction text. This has the benefit that if we actually need to generate a real relocation record, its address will come out correctly automatically, without having to fiddle with the offset in adjustFixupOffset. Tested on both 64-bit and 32-bit PowerPC, using external and integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -57,13 +57,13 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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case FK_Data_1:
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return 1;
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case FK_Data_2:
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case PPC::fixup_ppc_ha16:
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case PPC::fixup_ppc_lo16:
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case PPC::fixup_ppc_lo16_ds:
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return 2;
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case FK_Data_4:
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case PPC::fixup_ppc_brcond14:
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case PPC::fixup_ppc_br24:
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case PPC::fixup_ppc_ha16:
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case PPC::fixup_ppc_lo16:
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case PPC::fixup_ppc_lo16_ds:
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return 4;
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case FK_Data_8:
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return 8;
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@ -100,9 +100,9 @@ public:
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// name offset bits flags
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{ "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_lo16", 16, 16, 0 },
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{ "fixup_ppc_ha16", 16, 16, 0 },
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{ "fixup_ppc_lo16_ds", 16, 14, 0 },
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{ "fixup_ppc_lo16", 0, 16, 0 },
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{ "fixup_ppc_ha16", 0, 16, 0 },
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{ "fixup_ppc_lo16_ds", 0, 14, 0 },
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{ "fixup_ppc_tlsreg", 0, 0, 0 },
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{ "fixup_ppc_nofixup", 0, 0, 0 }
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};
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@ -33,7 +33,6 @@ namespace {
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virtual const MCSymbol *undefinedExplicitRelSym(const MCValue &Target,
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const MCFixup &Fixup,
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bool IsPCRel) const;
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virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset);
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virtual void sortRelocs(const MCAssembler &Asm,
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std::vector<ELFRelocationEntry> &Relocs);
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@ -240,19 +239,6 @@ const MCSymbol *PPCELFObjectWriter::undefinedExplicitRelSym(const MCValue &Targe
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return NULL;
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}
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void PPCELFObjectWriter::
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adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) {
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switch ((unsigned)Fixup.getKind()) {
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case PPC::fixup_ppc_ha16:
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case PPC::fixup_ppc_lo16:
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case PPC::fixup_ppc_lo16_ds:
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RelocOffset += 2;
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break;
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default:
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break;
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}
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}
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// The standard sorter only sorts on the r_offset field, but PowerPC can
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// have multiple relocations at the same offset. Sort secondarily on the
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// relocation type to avoid nondeterminism.
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@ -142,7 +142,7 @@ unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_ha16));
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return 0;
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}
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@ -153,7 +153,7 @@ unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
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// Add a fixup for the branch target.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo16));
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return 0;
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}
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@ -170,7 +170,7 @@ unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
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return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
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// Add a fixup for the displacement field.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo16));
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return RegBits;
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}
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@ -188,7 +188,7 @@ unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
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return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
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// Add a fixup for the displacement field.
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Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
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Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_lo16_ds));
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return RegBits;
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}
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@ -8,113 +8,113 @@
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# FIXME: .TOC.@tocbase
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# CHECK: li 3, target@l # encoding: [0x38,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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li 3, target@l
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# CHECK: addis 3, 3, target@ha # encoding: [0x3c,0x63,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_HA target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
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addis 3, 3, target@ha
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# CHECK: lis 3, target@ha # encoding: [0x3c,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_HA target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
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lis 3, target@ha
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# CHECK: addi 4, 3, target@l # encoding: [0x38,0x83,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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addi 4, 3, target@l
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# CHECK: lwz 1, target@l(3) # encoding: [0x80,0x23,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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lwz 1, target@l(3)
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# CHECK: ld 1, target@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16_ds
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO_DS target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16_ds
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0
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ld 1, target@l(3)
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# CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@toc, kind: fixup_ppc_lo16_ds
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_lo16_ds
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0
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ld 1, target@toc(2)
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# CHECK: addis 3, 2, target@toc@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0
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addis 3, 2, target@toc@ha
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# CHECK: addi 4, 3, target@toc@l # encoding: [0x38,0x83,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
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addi 4, 3, target@toc@l
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# CHECK: lwz 1, target@toc@l(3) # encoding: [0x80,0x23,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
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lwz 1, target@toc@l(3)
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# CHECK: ld 1, target@toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16_ds
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16_ds
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0
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ld 1, target@toc@l(3)
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# FIXME: @tls
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# CHECK: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@tprel@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0
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addis 3, 2, target@tprel@ha
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# CHECK: addi 3, 3, target@tprel@l # encoding: [0x38,0x63,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@tprel@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0
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addi 3, 3, target@tprel@l
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# CHECK: addis 3, 2, target@dtprel@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@dtprel@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_HA target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0
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addis 3, 2, target@dtprel@ha
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# CHECK: addi 3, 3, target@dtprel@l # encoding: [0x38,0x63,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@dtprel@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_LO target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0
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addi 3, 3, target@dtprel@l
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# CHECK: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tprel@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0
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addis 3, 2, target@got@tprel@ha
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# CHECK: ld 1, target@got@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
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ld 1, target@got@tprel@l(3)
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# CHECK: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0
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addis 3, 2, target@got@tlsgd@ha
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# CHECK: addi 3, 3, target@got@tlsgd@l # encoding: [0x38,0x63,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0
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addi 3, 3, target@got@tlsgd@l
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# CHECK: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsld@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_ha16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0
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addis 3, 2, target@got@tlsld@ha
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# CHECK: addi 3, 3, target@got@tlsld@l # encoding: [0x38,0x63,A,A]
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# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsld@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO target 0x0
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# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_lo16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0
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addi 3, 3, target@got@tlsld@l
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