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ARM64: Improve diagnostics for malformed reg+reg addressing mode.

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Make sure only general purpose registers are valid for offset regs and
that 32-bit regs are only valid for sxtw and uxtw extends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206799 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2014-04-21 21:45:57 +00:00
parent 8a412da0ea
commit 91c655736e
2 changed files with 24 additions and 1 deletions
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13
lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
View File

@ -1416,7 +1416,7 @@ public:
assert(N == 3 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
Inst.addOperand(MCOperand::CreateReg(getXRegFromWReg(Mem.OffsetRegNum)));
unsigned ExtendImm = ARM64_AM::getMemExtendImm(Mem.ExtType, DoShift);
Inst.addOperand(MCOperand::CreateImm(ExtendImm));
}
@ -2894,6 +2894,17 @@ bool ARM64AsmParser::parseMemory(OperandVector &Operands) {
Parser.Lex(); // Eat the extend op.
// A 32-bit offset register is only valid for [SU]/XTW extend
// operators.
if (isGPR32Register(Reg2)) {
if (ExtOp != ARM64_AM::UXTW &&
ExtOp != ARM64_AM::SXTW)
return Error(ExtLoc, "32-bit general purpose offset register "
"requires sxtw or uxtw extend");
} else if (!isGPR64Register(Reg2))
return Error(OffsetLoc,
"64-bit general purpose offset register expected");
bool Hash = getLexer().is(AsmToken::Hash);
if (getLexer().is(AsmToken::RBrac)) {
// No immediate operand.

12
test/MC/ARM64/diags.s
View File

@ -74,6 +74,18 @@ foo:
; CHECK-ERRORS: ^
; Check that register offset addressing modes only accept 32-bit offset
; registers when using uxtw/sxtw extends. Everything else requires a 64-bit
; register.
str d1, [x3, w3, sxtx #3]
ldr s1, [x3, d3, sxtx #2]
; CHECK-ERRORS: 32-bit general purpose offset register requires sxtw or uxtw extend
; CHECK-ERRORS: str d1, [x3, w3, sxtx #3]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: 64-bit general purpose offset register expected
; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2]
; CHECK-ERRORS: ^
; Shift immediates range checking.
sqrshrn b4, h9, #10