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[AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195936 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin
2013-11-29 01:29:16 +00:00
parent e9f8ce8cde
commit 9224192321
3 changed files with 90 additions and 35 deletions
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36
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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@@ -238,6 +238,10 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
static bool Check(DecodeStatus &Out, DecodeStatus In);
#include "AArch64GenDisassemblerTables.inc"
@@ -1534,3 +1538,35 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
return MCDisassembler::Success;
}
static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned Rd = fieldFromInstruction(Insn, 0, 5);
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
unsigned size = fieldFromInstruction(Insn, 22, 2);
unsigned Q = fieldFromInstruction(Insn, 30, 1);
DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
if(Q)
DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
else
DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder);
switch (size) {
case 0:
Inst.addOperand(MCOperand::CreateImm(8));
break;
case 1:
Inst.addOperand(MCOperand::CreateImm(16));
break;
case 2:
Inst.addOperand(MCOperand::CreateImm(32));
break;
default :
return MCDisassembler::Fail;
}
return MCDisassembler::Success;
}