mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-12 13:30:51 +00:00
Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174193 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
05f52eca94
commit
924223c9ab
@ -1500,26 +1500,11 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
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return Hexagon::JMPR_cPt;
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// V4 indexed+scaled load.
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case Hexagon::LDrid_indexed_cPt_V4:
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return Hexagon::LDrid_indexed_cNotPt_V4;
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case Hexagon::LDrid_indexed_cNotPt_V4:
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return Hexagon::LDrid_indexed_cPt_V4;
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case Hexagon::LDrid_indexed_shl_cPt_V4:
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return Hexagon::LDrid_indexed_shl_cNotPt_V4;
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case Hexagon::LDrid_indexed_shl_cNotPt_V4:
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return Hexagon::LDrid_indexed_shl_cPt_V4;
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case Hexagon::LDrib_indexed_cPt_V4:
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return Hexagon::LDrib_indexed_cNotPt_V4;
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case Hexagon::LDrib_indexed_cNotPt_V4:
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return Hexagon::LDrib_indexed_cPt_V4;
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case Hexagon::LDriub_indexed_cPt_V4:
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return Hexagon::LDriub_indexed_cNotPt_V4;
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case Hexagon::LDriub_indexed_cNotPt_V4:
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return Hexagon::LDriub_indexed_cPt_V4;
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case Hexagon::LDrib_indexed_shl_cPt_V4:
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return Hexagon::LDrib_indexed_shl_cNotPt_V4;
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case Hexagon::LDrib_indexed_shl_cNotPt_V4:
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@ -1530,16 +1515,6 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
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case Hexagon::LDriub_indexed_shl_cNotPt_V4:
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return Hexagon::LDriub_indexed_shl_cPt_V4;
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case Hexagon::LDrih_indexed_cPt_V4:
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return Hexagon::LDrih_indexed_cNotPt_V4;
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case Hexagon::LDrih_indexed_cNotPt_V4:
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return Hexagon::LDrih_indexed_cPt_V4;
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case Hexagon::LDriuh_indexed_cPt_V4:
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return Hexagon::LDriuh_indexed_cNotPt_V4;
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case Hexagon::LDriuh_indexed_cNotPt_V4:
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return Hexagon::LDriuh_indexed_cPt_V4;
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case Hexagon::LDrih_indexed_shl_cPt_V4:
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return Hexagon::LDrih_indexed_shl_cNotPt_V4;
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case Hexagon::LDrih_indexed_shl_cNotPt_V4:
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@ -1550,11 +1525,6 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
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case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
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return Hexagon::LDriuh_indexed_shl_cPt_V4;
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case Hexagon::LDriw_indexed_cPt_V4:
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return Hexagon::LDriw_indexed_cNotPt_V4;
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case Hexagon::LDriw_indexed_cNotPt_V4:
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return Hexagon::LDriw_indexed_cPt_V4;
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case Hexagon::LDriw_indexed_shl_cPt_V4:
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return Hexagon::LDriw_indexed_shl_cNotPt_V4;
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case Hexagon::LDriw_indexed_shl_cNotPt_V4:
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@ -1965,51 +1935,21 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
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Hexagon::JMPR_cNotPt;
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// V4 indexed+scaled load.
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case Hexagon::LDrid_indexed_V4:
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return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 :
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Hexagon::LDrid_indexed_cNotPt_V4;
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case Hexagon::LDrid_indexed_shl_V4:
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return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
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Hexagon::LDrid_indexed_shl_cNotPt_V4;
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case Hexagon::LDrib_indexed_V4:
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return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 :
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Hexagon::LDrib_indexed_cNotPt_V4;
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case Hexagon::LDriub_indexed_V4:
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return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
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Hexagon::LDriub_indexed_cNotPt_V4;
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case Hexagon::LDriub_ae_indexed_V4:
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return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
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Hexagon::LDriub_indexed_cNotPt_V4;
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case Hexagon::LDrib_indexed_shl_V4:
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return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
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Hexagon::LDrib_indexed_shl_cNotPt_V4;
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case Hexagon::LDriub_indexed_shl_V4:
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return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
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Hexagon::LDriub_indexed_shl_cNotPt_V4;
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case Hexagon::LDriub_ae_indexed_shl_V4:
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return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
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Hexagon::LDriub_indexed_shl_cNotPt_V4;
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case Hexagon::LDrih_indexed_V4:
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return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 :
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Hexagon::LDrih_indexed_cNotPt_V4;
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case Hexagon::LDriuh_indexed_V4:
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return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
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Hexagon::LDriuh_indexed_cNotPt_V4;
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case Hexagon::LDriuh_ae_indexed_V4:
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return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
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Hexagon::LDriuh_indexed_cNotPt_V4;
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case Hexagon::LDrih_indexed_shl_V4:
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return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
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Hexagon::LDrih_indexed_shl_cNotPt_V4;
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case Hexagon::LDriuh_indexed_shl_V4:
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return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
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Hexagon::LDriuh_indexed_shl_cNotPt_V4;
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case Hexagon::LDriuh_ae_indexed_shl_V4:
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return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
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Hexagon::LDriuh_indexed_shl_cNotPt_V4;
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case Hexagon::LDriw_indexed_V4:
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return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 :
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Hexagon::LDriw_indexed_cNotPt_V4;
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case Hexagon::LDriw_indexed_shl_V4:
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return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
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Hexagon::LDriw_indexed_shl_cNotPt_V4;
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@ -2647,28 +2587,16 @@ isConditionalLoad (const MachineInstr* MI) const {
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case Hexagon::POST_LDriub_cPt :
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case Hexagon::POST_LDriub_cNotPt :
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return QRI.Subtarget.hasV4TOps();
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case Hexagon::LDrid_indexed_cPt_V4 :
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case Hexagon::LDrid_indexed_cNotPt_V4 :
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case Hexagon::LDrid_indexed_shl_cPt_V4 :
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case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
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case Hexagon::LDrib_indexed_cPt_V4 :
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case Hexagon::LDrib_indexed_cNotPt_V4 :
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case Hexagon::LDrib_indexed_shl_cPt_V4 :
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case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
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case Hexagon::LDriub_indexed_cPt_V4 :
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case Hexagon::LDriub_indexed_cNotPt_V4 :
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case Hexagon::LDriub_indexed_shl_cPt_V4 :
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case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
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case Hexagon::LDrih_indexed_cPt_V4 :
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case Hexagon::LDrih_indexed_cNotPt_V4 :
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case Hexagon::LDrih_indexed_shl_cPt_V4 :
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case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
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case Hexagon::LDriuh_indexed_cPt_V4 :
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case Hexagon::LDriuh_indexed_cNotPt_V4 :
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case Hexagon::LDriuh_indexed_shl_cPt_V4 :
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case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
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case Hexagon::LDriw_indexed_cPt_V4 :
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case Hexagon::LDriw_indexed_cNotPt_V4 :
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case Hexagon::LDriw_indexed_shl_cPt_V4 :
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case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
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return QRI.Subtarget.hasV4TOps();
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@ -389,25 +389,6 @@ def LDriw_abs_set_V4 : LDInst2<(outs IntRegs:$dst1, IntRegs:$dst2),
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Requires<[HasV4T]>;
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}
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// Load doubleword.
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//
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// Make sure that in post increment load, the first operand is always the post
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// increment operand.
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//
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// Rdd=memd(Rs+Rt<<#u2)
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// Special case pattern for indexed load without offset which is easier to
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// match. AddedComplexity of this pattern should be lower than base+offset load
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// and lower yet than the more generic version with offset/shift below
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// Similar approach is taken for all other base+index loads.
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let AddedComplexity = 10, isPredicable = 1 in
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def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst=memd($src1+$src2<<#0)",
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[(set (i64 DoubleRegs:$dst),
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(i64 (load (add (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))))]>,
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Requires<[HasV4T]>;
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// multiclass for load instructions with base + register offset
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// addressing mode
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multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
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@ -506,314 +487,42 @@ def : Pat <(i64 (load (add IntRegs:$src1,
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Requires<[HasV4T]>;
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}
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//// Load doubleword conditionally.
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// if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2)
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// if (Pv) Rd=memd(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDrid_indexed_cPt_V4 : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1) $dst=memd($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) Rd=memd(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDrid_indexed_cdnPt_V4 : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1.new) $dst=memd($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) Rd=memd(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDrid_indexed_cNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1) $dst=memd($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) Rd=memd(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDrid_indexed_cdnNotPt_V4 : LDInst2<(outs DoubleRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1.new) $dst=memd($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// Rdd=memd(Rt<<#u2+#U6)
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//// Load byte.
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// Rd=memb(Rs+Rt<<#u2)
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let AddedComplexity = 10, isPredicable = 1 in
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def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst=memb($src1+$src2<<#0)",
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[(set (i32 IntRegs:$dst),
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(i32 (sextloadi8 (add (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 10, isPredicable = 1 in
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def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst=memub($src1+$src2<<#0)",
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[(set (i32 IntRegs:$dst),
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(i32 (zextloadi8 (add (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 10, isPredicable = 1 in
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def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst=memub($src1+$src2<<#0)",
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[(set (i32 IntRegs:$dst),
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(i32 (extloadi8 (add (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 40, isPredicable = 1 in
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def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
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"$dst=memub($src1+$src2<<#$offset)",
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[(set (i32 IntRegs:$dst),
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(i32 (extloadi8 (add (i32 IntRegs:$src1),
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(shl (i32 IntRegs:$src2),
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u2ImmPred:$offset)))))]>,
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Requires<[HasV4T]>;
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//// Load byte conditionally.
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// if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2)
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// if (Pv) Rd=memb(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDrib_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1) $dst=memb($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) Rd=memb(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDrib_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1.new) $dst=memb($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) Rd=memb(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDrib_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1) $dst=memb($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) Rd=memb(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDrib_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1.new) $dst=memb($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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//// Load unsigned byte conditionally.
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// if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2)
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// if (Pv) Rd=memub(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDriub_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1) $dst=memub($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// if (Pv.new) Rd=memub(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDriub_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if ($src1.new) $dst=memub($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv) Rd=memub(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDriub_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1) $dst=memub($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// if (!Pv.new) Rd=memub(Rs+Rt<<#u2)
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let AddedComplexity = 15, isPredicated = 1 in
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def LDriub_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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"if (!$src1.new) $dst=memub($src2+$src3<<#0)",
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[]>,
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Requires<[HasV4T]>;
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// Rd=memb(Rt<<#u2+#U6)
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//// Load halfword
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// Rd=memh(Rs+Rt<<#u2)
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let AddedComplexity = 10, isPredicable = 1 in
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def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst=memh($src1+$src2<<#0)",
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[(set (i32 IntRegs:$dst),
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(i32 (sextloadi16 (add (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 10, isPredicable = 1 in
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def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst=memuh($src1+$src2<<#0)",
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[(set (i32 IntRegs:$dst),
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(i32 (zextloadi16 (add (i32 IntRegs:$src1),
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(i32 IntRegs:$src2)))))]>,
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Requires<[HasV4T]>;
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let AddedComplexity = 10, isPredicable = 1 in
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def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins IntRegs:$src1, IntRegs:$src2),
|
||||
"$dst=memuh($src1+$src2<<#0)",
|
||||
[(set (i32 IntRegs:$dst),
|
||||
(i32 (extloadi16 (add (i32 IntRegs:$src1),
|
||||
(i32 IntRegs:$src2)))))]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let AddedComplexity = 40, isPredicable = 1 in
|
||||
def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
|
||||
"$dst=memuh($src1+$src2<<#$offset)",
|
||||
[(set (i32 IntRegs:$dst),
|
||||
(i32 (extloadi16 (add (i32 IntRegs:$src1),
|
||||
(shl (i32 IntRegs:$src2),
|
||||
u2ImmPred:$offset)))))]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
//// Load halfword conditionally.
|
||||
// if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2)
|
||||
// if (Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrih_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst=memh($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrih_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst=memh($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrih_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst=memh($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDrih_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst=memh($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
//// Load unsigned halfword conditionally.
|
||||
// if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2)
|
||||
// if (Pv) Rd=memuh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriuh_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst=memuh($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memuh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriuh_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst=memuh($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memuh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriuh_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst=memuh($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memuh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriuh_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst=memuh($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// Rd=memh(Rt<<#u2+#U6)
|
||||
|
||||
//// Load word.
|
||||
// Load predicate: Fix for bug 5279.
|
||||
let neverHasSideEffects = 1 in
|
||||
def LDriw_pred_V4 : LDInst2<(outs PredRegs:$dst),
|
||||
(ins MEMri:$addr),
|
||||
"Error; should not emit",
|
||||
[]>,
|
||||
// 'def pats' for load instruction base + register offset and
|
||||
// zero immediate value.
|
||||
let AddedComplexity = 10 in {
|
||||
def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))),
|
||||
(LDrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// Rd=memw(Re=#U6)
|
||||
def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
|
||||
(LDrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// Rd=memw(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 10, isPredicable = 1 in
|
||||
def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),
|
||||
(ins IntRegs:$src1, IntRegs:$src2),
|
||||
"$dst=memw($src1+$src2<<#0)",
|
||||
[(set (i32 IntRegs:$dst),
|
||||
(i32 (load (add (i32 IntRegs:$src1),
|
||||
(i32 IntRegs:$src2)))))]>,
|
||||
Requires<[HasV4T]>;
|
||||
def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))),
|
||||
(LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
//// Load word conditionally.
|
||||
// if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2)
|
||||
// if (Pv) Rd=memw(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriw_indexed_cPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1) $dst=memw($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))),
|
||||
(LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriw_indexed_cdnPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if ($src1.new) $dst=memw($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
|
||||
(LDrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriw_indexed_cNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1) $dst=memw($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))),
|
||||
(LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) Rd=memh(Rs+Rt<<#u2)
|
||||
let AddedComplexity = 15, isPredicated = 1 in
|
||||
def LDriw_indexed_cdnNotPt_V4 : LDInst2<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"if (!$src1.new) $dst=memw($src2+$src3<<#0)",
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))),
|
||||
(LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))),
|
||||
(LDriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
|
||||
/// Load from global offset
|
||||
|
||||
|
||||
@ -1092,72 +1092,36 @@ static int GetDotNewPredOp(const int opc) {
|
||||
|
||||
// V4 indexed+scaled load
|
||||
|
||||
case Hexagon::LDrid_indexed_cPt_V4 :
|
||||
return Hexagon::LDrid_indexed_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDrid_indexed_cNotPt_V4 :
|
||||
return Hexagon::LDrid_indexed_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDrid_indexed_shl_cPt_V4 :
|
||||
return Hexagon::LDrid_indexed_shl_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
|
||||
return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDrib_indexed_cPt_V4 :
|
||||
return Hexagon::LDrib_indexed_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDrib_indexed_cNotPt_V4 :
|
||||
return Hexagon::LDrib_indexed_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDrib_indexed_shl_cPt_V4 :
|
||||
return Hexagon::LDrib_indexed_shl_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
|
||||
return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDriub_indexed_cPt_V4 :
|
||||
return Hexagon::LDriub_indexed_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDriub_indexed_cNotPt_V4 :
|
||||
return Hexagon::LDriub_indexed_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDriub_indexed_shl_cPt_V4 :
|
||||
return Hexagon::LDriub_indexed_shl_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
|
||||
return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDrih_indexed_cPt_V4 :
|
||||
return Hexagon::LDrih_indexed_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDrih_indexed_cNotPt_V4 :
|
||||
return Hexagon::LDrih_indexed_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDrih_indexed_shl_cPt_V4 :
|
||||
return Hexagon::LDrih_indexed_shl_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
|
||||
return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDriuh_indexed_cPt_V4 :
|
||||
return Hexagon::LDriuh_indexed_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDriuh_indexed_cNotPt_V4 :
|
||||
return Hexagon::LDriuh_indexed_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDriuh_indexed_shl_cPt_V4 :
|
||||
return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
|
||||
return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDriw_indexed_cPt_V4 :
|
||||
return Hexagon::LDriw_indexed_cdnPt_V4;
|
||||
|
||||
case Hexagon::LDriw_indexed_cNotPt_V4 :
|
||||
return Hexagon::LDriw_indexed_cdnNotPt_V4;
|
||||
|
||||
case Hexagon::LDriw_indexed_shl_cPt_V4 :
|
||||
return Hexagon::LDriw_indexed_shl_cdnPt_V4;
|
||||
|
||||
@ -1623,72 +1587,36 @@ static int GetDotOldOp(const int opc) {
|
||||
|
||||
// V4 indexed+scaled Load
|
||||
|
||||
case Hexagon::LDrid_indexed_cdnPt_V4 :
|
||||
return Hexagon::LDrid_indexed_cPt_V4;
|
||||
|
||||
case Hexagon::LDrid_indexed_cdnNotPt_V4 :
|
||||
return Hexagon::LDrid_indexed_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
|
||||
return Hexagon::LDrid_indexed_shl_cPt_V4;
|
||||
|
||||
case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
|
||||
return Hexagon::LDrid_indexed_shl_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDrib_indexed_cdnPt_V4 :
|
||||
return Hexagon::LDrib_indexed_cPt_V4;
|
||||
|
||||
case Hexagon::LDrib_indexed_cdnNotPt_V4 :
|
||||
return Hexagon::LDrib_indexed_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
|
||||
return Hexagon::LDrib_indexed_shl_cPt_V4;
|
||||
|
||||
case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
|
||||
return Hexagon::LDrib_indexed_shl_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDriub_indexed_cdnPt_V4 :
|
||||
return Hexagon::LDriub_indexed_cPt_V4;
|
||||
|
||||
case Hexagon::LDriub_indexed_cdnNotPt_V4 :
|
||||
return Hexagon::LDriub_indexed_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
|
||||
return Hexagon::LDriub_indexed_shl_cPt_V4;
|
||||
|
||||
case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
|
||||
return Hexagon::LDriub_indexed_shl_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDrih_indexed_cdnPt_V4 :
|
||||
return Hexagon::LDrih_indexed_cPt_V4;
|
||||
|
||||
case Hexagon::LDrih_indexed_cdnNotPt_V4 :
|
||||
return Hexagon::LDrih_indexed_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
|
||||
return Hexagon::LDrih_indexed_shl_cPt_V4;
|
||||
|
||||
case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
|
||||
return Hexagon::LDrih_indexed_shl_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDriuh_indexed_cdnPt_V4 :
|
||||
return Hexagon::LDriuh_indexed_cPt_V4;
|
||||
|
||||
case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
|
||||
return Hexagon::LDriuh_indexed_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
|
||||
return Hexagon::LDriuh_indexed_shl_cPt_V4;
|
||||
|
||||
case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
|
||||
return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDriw_indexed_cdnPt_V4 :
|
||||
return Hexagon::LDriw_indexed_cPt_V4;
|
||||
|
||||
case Hexagon::LDriw_indexed_cdnNotPt_V4 :
|
||||
return Hexagon::LDriw_indexed_cNotPt_V4;
|
||||
|
||||
case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
|
||||
return Hexagon::LDriw_indexed_shl_cPt_V4;
|
||||
|
||||
@ -2249,28 +2177,16 @@ static bool GetPredicateSense(MachineInstr* MI,
|
||||
case Hexagon::LDriub_indexed_cdnPt :
|
||||
case Hexagon::POST_LDriub_cPt :
|
||||
case Hexagon::POST_LDriub_cdnPt_V4 :
|
||||
case Hexagon::LDrid_indexed_cPt_V4 :
|
||||
case Hexagon::LDrid_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDrib_indexed_cPt_V4 :
|
||||
case Hexagon::LDrib_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriub_indexed_cPt_V4 :
|
||||
case Hexagon::LDriub_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDrih_indexed_cPt_V4 :
|
||||
case Hexagon::LDrih_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_cPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriw_indexed_cPt_V4 :
|
||||
case Hexagon::LDriw_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::ADD_ri_cPt :
|
||||
@ -2420,28 +2336,16 @@ static bool GetPredicateSense(MachineInstr* MI,
|
||||
case Hexagon::LDriub_indexed_cdnNotPt :
|
||||
case Hexagon::POST_LDriub_cNotPt :
|
||||
case Hexagon::POST_LDriub_cdnNotPt_V4 :
|
||||
case Hexagon::LDrid_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDrid_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_cNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::ADD_ri_cNotPt :
|
||||
@ -2563,28 +2467,16 @@ bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
|
||||
case Hexagon::POST_LDriub_cdnPt_V4 :
|
||||
case Hexagon::POST_LDriub_cdnNotPt_V4 :
|
||||
|
||||
case Hexagon::LDrid_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDrid_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDrib_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDriub_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDrih_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_cdnPt_V4 :
|
||||
case Hexagon::LDriw_indexed_cdnNotPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
|
||||
case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user