6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-01 10:57:21 +00:00
Code Issues Projects Releases Wiki Activity

expand tblgen's support for instructions with implicit defs.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98900 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-03-18 23:57:40 +00:00
parent 6c6ba36493
commit 928795387f
2 changed files with 18 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
utils/TableGen/CodeGenDAGPatterns.cpp
View File

@ -1163,12 +1163,14 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
} else if (!InstInfo.ImplicitDefs.empty()) {
// If the instruction has implicit defs, the first one defines the result
// type.
assert(InstInfo.ImplicitDefs[0]->isSubClassOf("Register"));
Record *FirstImplicitDef = InstInfo.ImplicitDefs[0];
assert(FirstImplicitDef->isSubClassOf("Register"));
const std::vector<MVT::SimpleValueType> &RegVTs =
CDP.getTargetInfo().getRegisterVTs(FirstImplicitDef);
if (!RegVTs.empty())
if (RegVTs.size() == 1)
ResultType = EEVT::TypeSet(RegVTs);
else
ResultType = EEVT::TypeSet(MVT::isVoid, TP);
} else {
// Otherwise, the instruction produces no value result.
// FIXME: Model "no result" different than "one result that is void"

20
utils/TableGen/DAGISelMatcherGen.cpp
View File

@ -698,7 +698,7 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
// occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second,
PhysRegInputs[i].first));
PhysRegInputs[i].first));
// Even if the node has no other flag inputs, the resultant node must be
// flagged to the CopyFromReg nodes we just generated.
TreeHasInFlag = true;
@ -708,12 +708,11 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
// Determine the result types.
SmallVector<MVT::SimpleValueType, 4> ResultVTs;
if (NumResults != 0 && N->getType() != MVT::isVoid) {
if (N->getType() != MVT::isVoid) {
// FIXME2: If the node has multiple results, we should add them. For now,
// preserve existing behavior?!
ResultVTs.push_back(N->getType());
}
// If this is the root instruction of a pattern that has physical registers in
// its result pattern, add output VTs for them. For example, X86 has:
@ -721,9 +720,18 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
// This also handles implicit results like:
// (implicit EFLAGS)
if (isRoot && Pattern.getDstRegs().size() != 0) {
for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i)
if (Pattern.getDstRegs()[i]->isSubClassOf("Register"))
ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT));
// If the root came from an implicit def in the instruction handling stuff,
// don't re-add it.
Record *HandledReg = 0;
if (NumResults == 0 && N->getType() != MVT::isVoid &&
!II.ImplicitDefs.empty())
HandledReg = II.ImplicitDefs[0];
for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) {
Record *Reg = Pattern.getDstRegs()[i];
if (!Reg->isSubClassOf("Register") || Reg == HandledReg) continue;
ResultVTs.push_back(getRegisterValueType(Reg, CGT));
}
}
// FIXME2: Instead of using the isVariadic flag on the instruction, we should