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https://github.com/c64scene-ar/llvm-6502.git
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Introducing a new method of tracking register pressure. We can't
precisely track pressure on a selection DAG, but we can at least keep it balanced. This design accounts for various interesting aspects of selection DAGS: register and subregister copies, glued nodes, dead nodes, unused registers, etc. Added SUnit::NumRegDefsLeft and ScheduleDAGSDNodes::RegDefIter. Note: I disabled PrescheduleNodesWithMultipleUses when register pressure is enabled, based on no evidence other than I don't think it makes sense to have both enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124853 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
parent
f827cd717b
commit
92e946630d
@ -248,6 +248,7 @@ namespace llvm {
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unsigned NumSuccs; // # of SDep::Data sucss.
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unsigned NumPredsLeft; // # of preds not scheduled.
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unsigned NumSuccsLeft; // # of succs not scheduled.
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unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.
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unsigned short Latency; // Node latency.
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bool isCall : 1; // Is a function call.
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bool isTwoAddress : 1; // Is a two-address instruction.
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@ -276,7 +277,7 @@ namespace llvm {
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SUnit(SDNode *node, unsigned nodenum)
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: Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
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NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
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NumSuccsLeft(0), Latency(0),
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NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
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isCall(false), isTwoAddress(false), isCommutable(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false),
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isPending(false), isAvailable(false), isScheduled(false),
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@ -290,7 +291,7 @@ namespace llvm {
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SUnit(MachineInstr *instr, unsigned nodenum)
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: Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
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NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
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NumSuccsLeft(0), Latency(0),
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NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
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isCall(false), isTwoAddress(false), isCommutable(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false),
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isPending(false), isAvailable(false), isScheduled(false),
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@ -303,7 +304,7 @@ namespace llvm {
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SUnit()
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: Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
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NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
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NumSuccsLeft(0), Latency(0),
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NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
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isCall(false), isTwoAddress(false), isCommutable(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false),
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isPending(false), isAvailable(false), isScheduled(false),
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@ -347,7 +348,7 @@ namespace llvm {
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/// addPred - This adds the specified edge as a pred of the current node if
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/// not already. It also adds the current node as a successor of the
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/// specified node.
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void addPred(const SDep &D);
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bool addPred(const SDep &D);
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/// removePred - This removes the specified edge as a pred of the current
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/// node if it exists. It also removes the current node as a successor of
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@ -442,6 +443,8 @@ namespace llvm {
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bool hasReadyFilter() const { return HasReadyFilter; }
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virtual bool tracksRegPressure() const { return false; }
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virtual bool isReady(SUnit *) const {
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assert(!HasReadyFilter && "The ready filter must override isReady()");
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return true;
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@ -75,12 +75,12 @@ void ScheduleDAG::Run(MachineBasicBlock *bb,
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/// addPred - This adds the specified edge as a pred of the current node if
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/// not already. It also adds the current node as a successor of the
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/// specified node.
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void SUnit::addPred(const SDep &D) {
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bool SUnit::addPred(const SDep &D) {
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// If this node already has this depenence, don't add a redundant one.
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for (SmallVector<SDep, 4>::const_iterator I = Preds.begin(), E = Preds.end();
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I != E; ++I)
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if (*I == D)
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return;
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return false;
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// Now add a corresponding succ to N.
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SDep P = D;
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P.setSUnit(this);
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@ -106,6 +106,7 @@ void SUnit::addPred(const SDep &D) {
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this->setDepthDirty();
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N->setHeightDirty();
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}
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return true;
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}
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/// removePred - This removes the specified edge as a pred of the current
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@ -285,6 +286,7 @@ void SUnit::dumpAll(const ScheduleDAG *G) const {
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dbgs() << " # preds left : " << NumPredsLeft << "\n";
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dbgs() << " # succs left : " << NumSuccsLeft << "\n";
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dbgs() << " # rdefs left : " << NumRegDefsLeft << "\n";
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dbgs() << " Latency : " << Latency << "\n";
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dbgs() << " Depth : " << Depth << "\n";
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dbgs() << " Height : " << Height << "\n";
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@ -706,6 +706,8 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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} else {
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LoadSU = CreateNewSUnit(LoadNode);
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LoadNode->setNodeId(LoadSU->NodeNum);
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InitNumRegDefsLeft(LoadSU);
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ComputeLatency(LoadSU);
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}
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@ -722,6 +724,8 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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}
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if (TID.isCommutable())
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NewSU->isCommutable = true;
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InitNumRegDefsLeft(NewSU);
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ComputeLatency(NewSU);
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// Record all the edges to and from the old SU, by category.
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@ -772,6 +776,10 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
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RemovePred(SuccDep, D);
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D.setSUnit(NewSU);
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AddPred(SuccDep, D);
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// Balance register pressure.
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if (AvailableQueue->tracksRegPressure() && SuccDep->isScheduled
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&& !D.isCtrl() && NewSU->NumRegDefsLeft > 0)
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--NewSU->NumRegDefsLeft;
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}
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for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
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SDep D = ChainSuccs[i];
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@ -1436,6 +1444,8 @@ public:
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SU->NodeQueueId = 0;
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}
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bool tracksRegPressure() const { return TracksRegPressure; }
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void dumpRegPressure() const;
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bool HighRegPressure(const SUnit *SU) const;
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@ -1571,7 +1581,8 @@ void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) {
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// Add pseudo dependency edges for two-address nodes.
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AddPseudoTwoAddrDeps();
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// Reroute edges to nodes with multiple uses.
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PrescheduleNodesWithMultipleUses();
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if (!TracksRegPressure)
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PrescheduleNodesWithMultipleUses();
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// Calculate node priorities.
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CalculateSethiUllmanNumbers();
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}
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@ -1642,64 +1653,20 @@ bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const {
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if (I->isCtrl())
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continue;
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SUnit *PredSU = I->getSUnit();
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// NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
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// counts data deps. To be more precise, we could maintain a
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// NumDataSuccsLeft count.
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if (PredSU->NumSuccsLeft != PredSU->Succs.size()) {
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DEBUG(dbgs() << " SU(" << PredSU->NodeNum << ") live across SU("
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<< SU->NodeNum << ")\n");
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// NumRegDefsLeft is zero when enough uses of this node have been scheduled
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// to cover the number of registers defined (they are all live).
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if (PredSU->NumRegDefsLeft == 0) {
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continue;
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}
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const SDNode *PN = PredSU->getNode();
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if (!PN->isMachineOpcode()) {
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if (PN->getOpcode() == ISD::CopyFromReg) {
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EVT VT = PN->getValueType(0);
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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unsigned Cost = TLI->getRepRegClassCostFor(VT);
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if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
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return true;
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}
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continue;
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}
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unsigned POpc = PN->getMachineOpcode();
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if (POpc == TargetOpcode::IMPLICIT_DEF)
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continue;
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if (POpc == TargetOpcode::EXTRACT_SUBREG) {
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EVT VT = PN->getOperand(0).getValueType();
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for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
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RegDefPos.IsValid(); RegDefPos.Advance()) {
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EVT VT = RegDefPos.GetValue();
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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unsigned Cost = TLI->getRepRegClassCostFor(VT);
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// Check if this increases register pressure of the specific register
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// class to the point where it would cause spills.
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if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
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return true;
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continue;
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} else if (POpc == TargetOpcode::INSERT_SUBREG ||
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POpc == TargetOpcode::SUBREG_TO_REG) {
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EVT VT = PN->getValueType(0);
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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unsigned Cost = TLI->getRepRegClassCostFor(VT);
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// Check if this increases register pressure of the specific register
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// class to the point where it would cause spills.
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if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
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return true;
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continue;
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}
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unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
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for (unsigned i = 0; i != NumDefs; ++i) {
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EVT VT = PN->getValueType(i);
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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if (RegPressure[RCId] >= RegLimit[RCId])
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return true; // Reg pressure already high.
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unsigned Cost = TLI->getRepRegClassCostFor(VT);
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if (!PN->hasAnyUseOfValue(i))
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continue;
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// Check if this increases register pressure of the specific register
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// class to the point where it would cause spills.
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if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
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return true;
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}
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}
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return false;
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}
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@ -1725,80 +1692,64 @@ void RegReductionPQBase::ScheduledNode(SUnit *SU) {
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if (!TracksRegPressure)
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return;
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const SDNode *N = SU->getNode();
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if (!N->isMachineOpcode()) {
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if (N->getOpcode() != ISD::CopyToReg)
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return;
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} else {
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unsigned Opc = N->getMachineOpcode();
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if (Opc == TargetOpcode::EXTRACT_SUBREG ||
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Opc == TargetOpcode::INSERT_SUBREG ||
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Opc == TargetOpcode::SUBREG_TO_REG ||
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Opc == TargetOpcode::REG_SEQUENCE ||
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Opc == TargetOpcode::IMPLICIT_DEF)
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return;
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}
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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if (I->isCtrl())
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continue;
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SUnit *PredSU = I->getSUnit();
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// NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
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// counts data deps.
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if (PredSU->NumSuccsLeft != PredSU->Succs.size())
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continue;
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const SDNode *PN = PredSU->getNode();
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if (!PN->isMachineOpcode()) {
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if (PN->getOpcode() == ISD::CopyFromReg) {
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EVT VT = PN->getValueType(0);
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
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}
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// NumRegDefsLeft is zero when enough uses of this node have been scheduled
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// to cover the number of registers defined (they are all live).
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if (PredSU->NumRegDefsLeft == 0) {
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continue;
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}
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unsigned POpc = PN->getMachineOpcode();
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if (POpc == TargetOpcode::IMPLICIT_DEF)
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continue;
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if (POpc == TargetOpcode::EXTRACT_SUBREG) {
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EVT VT = PN->getOperand(0).getValueType();
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
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continue;
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} else if (POpc == TargetOpcode::INSERT_SUBREG ||
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POpc == TargetOpcode::SUBREG_TO_REG) {
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EVT VT = PN->getValueType(0);
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
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continue;
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}
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unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
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for (unsigned i = 0; i != NumDefs; ++i) {
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EVT VT = PN->getValueType(i);
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if (!PN->hasAnyUseOfValue(i))
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// FIXME: The ScheduleDAG currently loses information about which of a
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// node's values is consumed by each dependence. Consequently, if the node
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// defines multiple register classes, we don't know which to pressurize
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// here. Instead the following loop consumes the register defs in an
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// arbitrary order. At least it handles the common case of clustered loads
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// to the same class. For precise liveness, each SDep needs to indicate the
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// result number. But that tightly couples the ScheduleDAG with the
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// SelectionDAG making updates tricky. A simpler hack would be to attach a
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// value type or register class to SDep.
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//
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// The most important aspect of register tracking is balancing the increase
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// here with the reduction further below. Note that this SU may use multiple
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// defs in PredSU. The can't be determined here, but we've already
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// compensated by reducing NumRegDefsLeft in PredSU during
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// ScheduleDAGSDNodes::AddSchedEdges.
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--PredSU->NumRegDefsLeft;
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unsigned SkipRegDefs = PredSU->NumRegDefsLeft;
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for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
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RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) {
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if (SkipRegDefs)
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continue;
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EVT VT = RegDefPos.GetValue();
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
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break;
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}
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}
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// Check for isMachineOpcode() as PrescheduleNodesWithMultipleUses()
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// may transfer data dependencies to CopyToReg.
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if (SU->NumSuccs && N->isMachineOpcode()) {
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unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
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for (unsigned i = 0; i != NumDefs; ++i) {
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EVT VT = N->getValueType(i);
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if (!N->hasAnyUseOfValue(i))
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continue;
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT))
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// Register pressure tracking is imprecise. This can happen.
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RegPressure[RCId] = 0;
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else
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RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
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// We should have this assert, but there may be dead SDNodes that never
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// materialize as SUnits, so they don't appear to generate liveness.
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//assert(SU->NumRegDefsLeft == 0 && "not all regdefs have scheduled uses");
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int SkipRegDefs = (int)SU->NumRegDefsLeft;
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for (ScheduleDAGSDNodes::RegDefIter RegDefPos(SU, scheduleDAG);
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RegDefPos.IsValid(); RegDefPos.Advance(), --SkipRegDefs) {
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if (SkipRegDefs > 0)
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continue;
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EVT VT = RegDefPos.GetValue();
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unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
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if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT)) {
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// Register pressure tracking is imprecise. This can happen. But we try
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// hard not to let it happen because it likely results in poor scheduling.
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DEBUG(dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n");
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RegPressure[RCId] = 0;
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}
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else {
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RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
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}
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}
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dumpRegPressure();
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}
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@ -2314,7 +2265,7 @@ void RegReductionPQBase::PrescheduleNodesWithMultipleUses() {
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if (PredSU->NumSuccs == 1)
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continue;
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// Avoid prescheduling to copies from virtual registers, which don't behave
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// like other nodes from the perspective of scheduling // heuristics.
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// like other nodes from the perspective of scheduling heuristics.
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if (SDNode *N = SU->getNode())
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if (N->getOpcode() == ISD::CopyFromReg &&
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TargetRegisterInfo::isVirtualRegister
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@ -332,6 +332,9 @@ void ScheduleDAGSDNodes::BuildSchedUnits() {
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NodeSUnit->NodeNum);
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// Compute NumRegDefsLeft. This must be done before AddSchedEdges.
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InitNumRegDefsLeft(NodeSUnit);
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// Assign the Latency field of NodeSUnit using target-provided information.
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ComputeLatency(NodeSUnit);
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}
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@ -407,7 +410,13 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
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ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep));
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}
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SU->addPred(dep);
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if (!SU->addPred(dep) && !dep.isCtrl() && OpSU->NumRegDefsLeft > 0) {
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// Multiple register uses are combined in the same SUnit. For example,
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// we could have a set of glued nodes with all their defs consumed by
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// another set of glued nodes. Register pressure tracking sees this as
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// a single use, so to keep pressure balanced we reduce the defs.
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--OpSU->NumRegDefsLeft;
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}
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}
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}
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}
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@ -426,6 +435,69 @@ void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
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AddSchedEdges();
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}
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// Initialize NumNodeDefs for the current Node's opcode.
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void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
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if (!Node->isMachineOpcode()) {
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if (Node->getOpcode() == ISD::CopyFromReg)
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NodeNumDefs = 1;
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else
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NodeNumDefs = 0;
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return;
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}
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unsigned POpc = Node->getMachineOpcode();
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if (POpc == TargetOpcode::IMPLICIT_DEF) {
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// No register need be allocated for this.
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NodeNumDefs = 0;
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return;
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}
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unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
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// Some instructions define regs that are not represented in the selection DAG
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// (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
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NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
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DefIdx = 0;
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}
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|
||||
// Construct a RegDefIter for this SUnit and find the first valid value.
|
||||
ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
|
||||
const ScheduleDAGSDNodes *SD)
|
||||
: SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
|
||||
InitNodeNumDefs();
|
||||
Advance();
|
||||
}
|
||||
|
||||
// Advance to the next valid value defined by the SUnit.
|
||||
void ScheduleDAGSDNodes::RegDefIter::Advance() {
|
||||
for (;Node;) { // Visit all glued nodes.
|
||||
for (;DefIdx < NodeNumDefs; ++DefIdx) {
|
||||
if (!Node->hasAnyUseOfValue(DefIdx))
|
||||
continue;
|
||||
if (Node->isMachineOpcode() &&
|
||||
Node->getMachineOpcode() == TargetOpcode::EXTRACT_SUBREG) {
|
||||
// Propagate the incoming (full-register) type. I doubt it's needed.
|
||||
ValueType = Node->getOperand(0).getValueType();
|
||||
}
|
||||
else {
|
||||
ValueType = Node->getValueType(DefIdx);
|
||||
}
|
||||
++DefIdx;
|
||||
return; // Found a normal regdef.
|
||||
}
|
||||
Node = Node->getGluedNode();
|
||||
if (Node == NULL) {
|
||||
return; // No values left to visit.
|
||||
}
|
||||
InitNodeNumDefs();
|
||||
}
|
||||
}
|
||||
|
||||
void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
|
||||
assert(SU->NumRegDefsLeft == 0 && "expect a new node");
|
||||
for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
|
||||
assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
|
||||
++SU->NumRegDefsLeft;
|
||||
}
|
||||
}
|
||||
|
||||
void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
|
||||
// Check to see if the scheduler cares about latencies.
|
||||
if (ForceUnitLatencies()) {
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
|
||||
namespace llvm {
|
||||
/// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
|
||||
///
|
||||
///
|
||||
/// Edges between SUnits are initially based on edges in the SelectionDAG,
|
||||
/// and additional edges can be added by the schedulers as heuristics.
|
||||
/// SDNodes such as Constants, Registers, and a few others that are not
|
||||
@ -73,13 +73,17 @@ namespace llvm {
|
||||
/// predecessors / successors info nor the temporary scheduling states.
|
||||
///
|
||||
SUnit *Clone(SUnit *N);
|
||||
|
||||
|
||||
/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
|
||||
/// are input. This SUnit graph is similar to the SelectionDAG, but
|
||||
/// excludes nodes that aren't interesting to scheduling, and represents
|
||||
/// flagged together nodes with a single SUnit.
|
||||
virtual void BuildSchedGraph(AliasAnalysis *AA);
|
||||
|
||||
/// InitNumRegDefsLeft - Determine the # of regs defined by this node.
|
||||
///
|
||||
void InitNumRegDefsLeft(SUnit *SU);
|
||||
|
||||
/// ComputeLatency - Compute node latency.
|
||||
///
|
||||
virtual void ComputeLatency(SUnit *SU);
|
||||
@ -106,6 +110,30 @@ namespace llvm {
|
||||
|
||||
virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
|
||||
|
||||
/// RegDefIter - In place iteration over the values defined by an
|
||||
/// SUnit. This does not need copies of the iterator or any other STLisms.
|
||||
/// The iterator creates itself, rather than being provided by the SchedDAG.
|
||||
class RegDefIter {
|
||||
const ScheduleDAGSDNodes *SchedDAG;
|
||||
const SDNode *Node;
|
||||
unsigned DefIdx;
|
||||
unsigned NodeNumDefs;
|
||||
EVT ValueType;
|
||||
public:
|
||||
RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
|
||||
|
||||
bool IsValid() const { return Node != NULL; }
|
||||
|
||||
EVT GetValue() const {
|
||||
assert(IsValid() && "bad iterator");
|
||||
return ValueType;
|
||||
}
|
||||
|
||||
void Advance();
|
||||
private:
|
||||
void InitNodeNumDefs();
|
||||
};
|
||||
|
||||
private:
|
||||
/// ClusterNeighboringLoads - Cluster loads from "near" addresses into
|
||||
/// combined SUnits.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user