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Add new node, SELECT_CC. This node is for targets that don't natively
implement SELECT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22755 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -183,6 +183,19 @@ public:
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ISD::CondCode Cond) {
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return getNode(ISD::SETCC, VT, LHS, RHS, getCondCode(Cond));
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}
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/// getSelectCC - Helper function to make it easier to build SelectCC's if you
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/// just have an ISD::CondCode instead of an SDOperand.
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///
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SDOperand getSelectCC(SDOperand LHS, SDOperand RHS,
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SDOperand True, SDOperand False, ISD::CondCode Cond) {
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MVT::ValueType VT = True.getValueType();
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assert(LHS.getValueType() == RHS.getValueType() &&
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"LHS and RHS of condition must have same type!");
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assert(True.getValueType() == False.getValueType() &&
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"True and False arms of SelectCC must have same type!");
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return getNode(ISD::SELECT_CC, VT, LHS, RHS, True, False,getCondCode(Cond));
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}
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/// getLoad - Loads are not normal binary operators: their result type is not
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/// determined by their operands, and they produce a value AND a token chain.
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@ -103,8 +103,14 @@ namespace ISD {
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// Counting operators
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CTTZ, CTLZ, CTPOP,
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// Select operator.
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SELECT,
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// Select
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SELECT,
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// Select with condition operator - This selects between a true value and
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// a false value (ops #2 and #3) based on the boolean result of comparing
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// the lhs and rhs (ops #0 and #1) of a conditional expression with the
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// condition code in op #4, a CondCodeSDNode.
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SELECT_CC,
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// SetCC operator - This evaluates to a boolean (i1) true value if the
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// condition is true. The operands to this are the left and right operands
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@ -362,7 +362,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
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if (I != LegalizedNodes.end()) return I->second;
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SDOperand Tmp1, Tmp2, Tmp3;
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SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
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SDOperand Result = Op;
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@ -911,6 +911,17 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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switch (TLI.getOperationAction(Node->getOpcode(), Tmp2.getValueType())) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Expand:
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if (Tmp1.getOpcode() == ISD::SETCC) {
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Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
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Tmp2, Tmp3,
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cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
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} else {
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Result = DAG.getSelectCC(Tmp1,
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DAG.getConstant(0, Tmp1.getValueType()),
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Tmp2, Tmp3, ISD::SETNE);
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}
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break;
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case TargetLowering::Legal:
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if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
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Tmp3 != Node->getOperand(2))
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@ -938,6 +949,29 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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}
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}
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break;
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case ISD::SELECT_CC:
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Tmp3 = LegalizeOp(Node->getOperand(2)); // True
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Tmp4 = LegalizeOp(Node->getOperand(3)); // False
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if (getTypeAction(Node->getOperand(0).getValueType()) == Legal) {
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Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
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Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
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if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
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Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
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Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2,
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Tmp3, Tmp4, Node->getOperand(4));
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}
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break;
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} else {
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Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
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Node->getOperand(0), // LHS
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Node->getOperand(1), // RHS
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Node->getOperand(4)));
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Result = DAG.getSelectCC(Tmp1,
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DAG.getConstant(0, Tmp1.getValueType()),
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Tmp3, Tmp4, ISD::SETNE);
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}
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break;
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case ISD::SETCC:
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Legal:
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@ -1999,6 +2033,13 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
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Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
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Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
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break;
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case ISD::SELECT_CC:
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Tmp2 = PromoteOp(Node->getOperand(2)); // True
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Tmp3 = PromoteOp(Node->getOperand(3)); // False
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Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
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Node->getOperand(1), Tmp2, Tmp3,
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Node->getOperand(4));
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break;
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case ISD::TAILCALL:
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case ISD::CALL: {
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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@ -2733,6 +2774,16 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
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break;
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}
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case ISD::SELECT_CC: {
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SDOperand TL, TH, FL, FH;
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ExpandOp(Node->getOperand(2), TL, TH);
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ExpandOp(Node->getOperand(3), FL, FH);
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Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
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Node->getOperand(1), TL, FL, Node->getOperand(4));
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Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
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Node->getOperand(1), TH, FH, Node->getOperand(4));
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break;
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}
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case ISD::SIGN_EXTEND: {
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SDOperand In;
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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@ -686,8 +686,6 @@ SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,
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return SDOperand();
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}
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/// getNode - Gets or creates the specified node.
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///
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SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) {
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@ -1702,6 +1700,7 @@ const char *SDNode::getOperationName() const {
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case ISD::SETCC: return "setcc";
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case ISD::SELECT: return "select";
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case ISD::SELECT_CC: return "select_cc";
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case ISD::ADD_PARTS: return "add_parts";
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case ISD::SUB_PARTS: return "sub_parts";
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case ISD::SHL_PARTS: return "shl_parts";
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