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MIR Parser: make the machine instruction parsing interface more consistent. NFC.

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This commit refactors the interface for machine instruction parser. It adopts
the pattern of returning a bool and passing in the result in the first argument
that is used by the other parsing methods for the the method 'parse' and the
function 'parseMachineInstr'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241085 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alex Lorenz 2015-06-30 17:47:50 +00:00
parent 8f1e30d67c
commit 939f023bf9
3 changed files with 26 additions and 30 deletions
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36
lib/CodeGen/MIRParser/MIParser.cpp
View File

@ -63,7 +63,7 @@ public:
/// This function always return true. /// This function always return true.
bool error(StringRef::iterator Loc, const Twine &Msg); bool error(StringRef::iterator Loc, const Twine &Msg);
MachineInstr *parse(); bool parse(MachineInstr *&MI);
bool parseRegister(unsigned &Reg); bool parseRegister(unsigned &Reg);
bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false); bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
@ -129,7 +129,7 @@ bool MIParser::error(StringRef::iterator Loc, const Twine &Msg) {
return true; return true;
} }
MachineInstr *MIParser::parse() { bool MIParser::parse(MachineInstr *&MI) {
lex(); lex();
// Parse any register operands before '=' // Parse any register operands before '='
@ -138,32 +138,28 @@ MachineInstr *MIParser::parse() {
SmallVector<MachineOperand, 8> Operands; SmallVector<MachineOperand, 8> Operands;
if (Token.isRegister()) { if (Token.isRegister()) {
if (parseRegisterOperand(MO, /*IsDef=*/true)) if (parseRegisterOperand(MO, /*IsDef=*/true))
return nullptr; return true;
Operands.push_back(MO); Operands.push_back(MO);
if (Token.isNot(MIToken::equal)) { if (Token.isNot(MIToken::equal))
error("expected '='"); return error("expected '='");
return nullptr;
}
lex(); lex();
} }
unsigned OpCode; unsigned OpCode;
if (Token.isError() || parseInstruction(OpCode)) if (Token.isError() || parseInstruction(OpCode))
return nullptr; return true;
// TODO: Parse the instruction flags and memory operands. // TODO: Parse the instruction flags and memory operands.
// Parse the remaining machine operands. // Parse the remaining machine operands.
while (Token.isNot(MIToken::Eof)) { while (Token.isNot(MIToken::Eof)) {
if (parseMachineOperand(MO)) if (parseMachineOperand(MO))
return nullptr; return true;
Operands.push_back(MO); Operands.push_back(MO);
if (Token.is(MIToken::Eof)) if (Token.is(MIToken::Eof))
break; break;
if (Token.isNot(MIToken::comma)) { if (Token.isNot(MIToken::comma))
error("expected ',' before the next machine operand"); return error("expected ',' before the next machine operand");
return nullptr;
}
lex(); lex();
} }
@ -184,10 +180,10 @@ MachineInstr *MIParser::parse() {
// TODO: Determine the implicit behaviour when implicit register flags are // TODO: Determine the implicit behaviour when implicit register flags are
// parsed. // parsed.
auto *MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true); MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);
for (const auto &Operand : Operands) for (const auto &Operand : Operands)
MI->addOperand(MF, Operand); MI->addOperand(MF, Operand);
return MI; return false;
} }
bool MIParser::parseInstruction(unsigned &OpCode) { bool MIParser::parseInstruction(unsigned &OpCode) {
@ -390,9 +386,9 @@ const uint32_t *MIParser::getRegMask(StringRef Identifier) {
return RegMaskInfo->getValue(); return RegMaskInfo->getValue();
} }
MachineInstr * bool llvm::parseMachineInstr(
llvm::parseMachineInstr(SourceMgr &SM, MachineFunction &MF, StringRef Src, MachineInstr *&MI, SourceMgr &SM, MachineFunction &MF, StringRef Src,
const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots, const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots,
const SlotMapping &IRSlots, SMDiagnostic &Error) { const SlotMapping &IRSlots, SMDiagnostic &Error) {
return MIParser(SM, MF, Error, Src, MBBSlots, IRSlots).parse(); return MIParser(SM, MF, Error, Src, MBBSlots, IRSlots).parse(MI);
} }

8
lib/CodeGen/MIRParser/MIParser.h
View File

@ -26,10 +26,10 @@ struct SlotMapping;
class SMDiagnostic; class SMDiagnostic;
class SourceMgr; class SourceMgr;
MachineInstr * bool parseMachineInstr(MachineInstr *&MI, SourceMgr &SM, MachineFunction &MF,
parseMachineInstr(SourceMgr &SM, MachineFunction &MF, StringRef Src, StringRef Src,
const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots, const DenseMap<unsigned, MachineBasicBlock *> &MBBSlots,
const SlotMapping &IRSlots, SMDiagnostic &Error); const SlotMapping &IRSlots, SMDiagnostic &Error);
} // end namespace llvm } // end namespace llvm

12
lib/CodeGen/MIRParser/MIRParser.cpp
View File

@ -265,13 +265,13 @@ bool MIRParserImpl::initializeMachineBasicBlock(
// Parse the instructions. // Parse the instructions.
for (const auto &MISource : YamlMBB.Instructions) { for (const auto &MISource : YamlMBB.Instructions) {
SMDiagnostic Error; SMDiagnostic Error;
if (auto *MI = parseMachineInstr(SM, MF, MISource.Value, MBBSlots, IRSlots, MachineInstr *MI = nullptr;
Error)) { if (parseMachineInstr(MI, SM, MF, MISource.Value, MBBSlots, IRSlots,
MBB.insert(MBB.end(), MI); Error)) {
continue; reportDiagnostic(diagFromMIStringDiag(Error, MISource.SourceRange));
return true;
} }
reportDiagnostic(diagFromMIStringDiag(Error, MISource.SourceRange)); MBB.insert(MBB.end(), MI);
return true;
} }
return false; return false;
} }