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Added support for splitting and scalarizing vector shifts.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61050 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang 2008-12-15 21:44:00 +00:00
parent 344b41cfbd
commit 93b3b928d7
4 changed files with 41 additions and 0 deletions
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1
lib/CodeGen/SelectionDAG/LegalizeTypes.h
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@ -496,6 +496,7 @@ private:
// Vector Result Scalarization: <1 x ty> -> ty.
void ScalarizeVectorResult(SDNode *N, unsigned OpNo);
SDValue ScalarizeVecRes_BinOp(SDNode *N);
SDValue ScalarizeVecRes_ShiftOp(SDNode *N);
SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
SDValue ScalarizeVecRes_BIT_CONVERT(SDNode *N);

18
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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@ -91,6 +91,10 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::UDIV:
case ISD::UREM:
case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
case ISD::SHL:
case ISD::SRA:
case ISD::SRL: R = ScalarizeVecRes_ShiftOp(N); break;
}
// If R is null, the sub-method took care of registering the result.
@ -104,6 +108,17 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) {
SDValue LHS = GetScalarizedVector(N->getOperand(0));
SDValue ShiftAmt = GetScalarizedVector(N->getOperand(1));
if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
ShiftAmt = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
else if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
ShiftAmt = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt);
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
MVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
@ -392,6 +407,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::AND:
case ISD::OR:
case ISD::XOR:
case ISD::SHL:
case ISD::SRA:
case ISD::SRL:
case ISD::UREM:
case ISD::SREM:
case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;

11
test/CodeGen/X86/vshift_scalar.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llvm-as < %s | llc
; Legalization test that requires scalarizing a vector.
define void @update(<1 x i32> %val, <1 x i32>* %dst) nounwind {
entry:
%shl = shl <1 x i32> %val, < i32 2>
%shr = ashr <1 x i32> %val, < i32 4>
store <1 x i32> %shr, <1 x i32>* %dst
ret void
}

11
test/CodeGen/X86/vshift_split2.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llvm-as < %s | llc
; Legalization example that requires splitting a large vector into smaller pieces.
define void @update(<8 x i32> %val, <8 x i32>* %dst) nounwind {
entry:
%shl = shl <8 x i32> %val, < i32 2, i32 2, i32 2, i32 2, i32 4, i32 4, i32 4, i32 4 >
%shr = ashr <8 x i32> %val, < i32 2, i32 2, i32 2, i32 2, i32 4, i32 4, i32 4, i32 4 >
store <8 x i32> %shr, <8 x i32>* %dst
ret void
}