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Fix the handling of edge cases in ARM shifted operands.

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This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris Lidbury.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
2012-09-22 11:18:12 +00:00
parent 23bd47c2d6
commit 93c7c449a1
6 changed files with 151 additions and 8 deletions
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lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+5
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@@ -1523,6 +1523,8 @@ DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
}
unsigned amt = fieldFromInstruction(Insn, 7, 5);
if (Opc == ARM_AM::ror && amt == 0)
Opc = ARM_AM::rrx;
unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
Inst.addOperand(MCOperand::CreateImm(imm));
@@ -1564,6 +1566,9 @@ static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
break;
}
if (ShOp == ARM_AM::ror && imm == 0)
ShOp = ARM_AM::rrx;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))