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Also add <imp-def> operands for defined and dead super-registers when rewriting.
We cannot rely on the <imp-def> operands added by LiveIntervals in all cases as demonstrated by the test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130313 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -260,6 +260,8 @@ void VirtRegMap::rewrite(SlotIndexes *Indexes) {
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<< "********** Function: "
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<< MF->getFunction()->getName() << '\n');
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DEBUG(dump());
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SmallVector<unsigned, 8> SuperDeads;
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SmallVector<unsigned, 8> SuperDefs;
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SmallVector<unsigned, 8> SuperKills;
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for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
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@ -283,12 +285,13 @@ void VirtRegMap::rewrite(SlotIndexes *Indexes) {
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if (MO.getSubReg()) {
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// A virtual register kill refers to the whole register, so we may
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// have to add <imp-use,kill> operands for the super-register.
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if (MO.isUse() && MO.isKill() && !MO.isUndef())
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SuperKills.push_back(PhysReg);
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// We don't have to deal with sub-register defs because
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// LiveIntervalAnalysis already added the necessary <imp-def>
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// operands.
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if (MO.isUse()) {
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if (MO.isKill() && !MO.isUndef())
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SuperKills.push_back(PhysReg);
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} else if (MO.isDead())
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SuperDeads.push_back(PhysReg);
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else
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SuperDefs.push_back(PhysReg);
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// PhysReg operands cannot have subregister indexes.
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PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
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@ -305,6 +308,12 @@ void VirtRegMap::rewrite(SlotIndexes *Indexes) {
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while (!SuperKills.empty())
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MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
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while (!SuperDeads.empty())
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MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
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while (!SuperDefs.empty())
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MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
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DEBUG(dbgs() << "> " << *MI);
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// Finally, remove any identity copies.
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@ -1,4 +1,4 @@
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; RUN: llc < %s -regalloc=greedy -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s
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; RUN: llc < %s -regalloc=greedy -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -verify-machineinstrs | FileCheck %s
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;
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; ARM tests that crash or fail with the greedy register allocator.
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@ -59,3 +59,26 @@ for.end: ; preds = %cond.end
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ret void
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}
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; CHECK: insert_elem
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; This test has a sub-register copy with a kill flag:
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; %vreg6:ssub_3<def> = COPY %vreg6:ssub_2<kill>; QPR_VFP2:%vreg6
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; The rewriter must do something sensible with that, or the scavenger crashes.
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define void @insert_elem() nounwind {
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entry:
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br i1 undef, label %if.end251, label %if.then84
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if.then84: ; preds = %entry
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br i1 undef, label %if.end251, label %if.then195
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if.then195: ; preds = %if.then84
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%div = fdiv float 1.000000e+00, undef
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%vecinit207 = insertelement <4 x float> undef, float %div, i32 1
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%vecinit208 = insertelement <4 x float> %vecinit207, float 1.000000e+00, i32 2
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%vecinit209 = insertelement <4 x float> %vecinit208, float 1.000000e+00, i32 3
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%mul216 = fmul <4 x float> zeroinitializer, %vecinit209
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store <4 x float> %mul216, <4 x float>* undef, align 16
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br label %if.end251
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if.end251: ; preds = %if.then195, %if.then84, %entry
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ret void
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}
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