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Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested

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was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2008-08-26 18:03:31 +00:00
parent a0b3909d43
commit 940f83e772
18 changed files with 78 additions and 59 deletions
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2
include/llvm/Target/TargetInstrInfo.h
View File

@ -221,7 +221,7 @@ public:
}
/// copyRegToReg - Add a copy between a pair of registers
virtual void copyRegToReg(MachineBasicBlock &MBB,
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,

10
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -250,9 +250,6 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
// Unhandled type. Halt "fast" selection and bail.
return I;
if (!TLI.isConvertLegal(SrcVT, DstVT))
// Illegal conversion. Halt "fast" selection and bail.
return I;
// Otherwise, insert a register-to-register copy.
TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
@ -264,9 +261,12 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
// Unhandled operand. Halt "fast" selection and bail.
return false;
TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Op0, DstClass, SrcClass);
ValueMap[I] = ResultReg;
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
Op0, DstClass, SrcClass);
if (!InsertedCopy)
return I;
ValueMap[I] = ResultReg;
break;
} else
// TODO: Casting a non-integral constant?

10
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -459,14 +459,14 @@ unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *T
return 2;
}
void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
cerr << "Not yet supported!";
abort();
// Not yet supported!
return false;
}
if (DestRC == ARM::GPRRegisterClass) {
@ -484,7 +484,9 @@ void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
.addReg(SrcReg));
else
abort();
return false;
return true;
}
static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,

2
lib/Target/ARM/ARMInstrInfo.h
View File

@ -163,7 +163,7 @@ public:
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB,
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,

12
lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -133,15 +133,15 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
return 2;
}
void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
//cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
if (DestRC != SrcRC) {
cerr << "Not yet supported!";
abort();
// Not yet supported!
return false;
}
if (DestRC == Alpha::GPRCRegisterClass) {
@ -151,9 +151,11 @@ void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
} else if (DestRC == Alpha::F8RCRegisterClass) {
BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
cerr << "Attempt to copy register that is not GPR or FPR";
abort();
// Attempt to copy register that is not GPR or FPR
return false;
}
return true;
}
void

2
lib/Target/Alpha/AlphaInstrInfo.h
View File

@ -42,7 +42,7 @@ public:
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB,
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,

8
lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -180,7 +180,7 @@ SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
return 0;
}
void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
@ -218,9 +218,11 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
.addReg(SrcReg);
} else {
cerr << "Attempt to copy unknown/unsupported register class!\n";
abort();
// Attempt to copy unknown/unsupported register class!
return false;
}
return true;
}
void

2
lib/Target/CellSPU/SPUInstrInfo.h
View File

@ -46,7 +46,7 @@ namespace llvm {
unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
virtual void copyRegToReg(MachineBasicBlock &MBB,
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,

8
lib/Target/IA64/IA64InstrInfo.cpp
View File

@ -57,14 +57,14 @@ IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
return 1;
}
void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
cerr << "Not yet supported!";
abort();
// Not yet supported!
return false;
}
if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
@ -73,6 +73,8 @@ void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
.addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
else // otherwise, MOV works (for both gen. regs and FP regs)
BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
return true;
}
void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,

2
lib/Target/IA64/IA64InstrInfo.h
View File

@ -40,7 +40,7 @@ public:
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB,
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,

16
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -118,7 +118,7 @@ insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
BuildMI(MBB, MI, get(Mips::NOP));
}
void MipsInstrInfo::
bool MipsInstrInfo::
copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
@ -141,10 +141,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
else if ((SrcRC == Mips::CCRRegisterClass) &&
(SrcReg == Mips::FCR31))
return; // This register is used implicitly, no copy needed.
return true; // This register is used implicitly, no copy needed.
else if ((DestRC == Mips::CCRRegisterClass) &&
(DestReg == Mips::FCR31))
return; // This register is used implicitly, no copy needed.
return true; // This register is used implicitly, no copy needed.
else if ((DestRC == Mips::HILORegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass)) {
unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
@ -154,9 +154,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
BuildMI(MBB, I, get(Opc), DestReg);
} else
assert (0 && "DestRC != SrcRC, Can't copy this register");
// DestRC != SrcRC, Can't copy this register
return false;
return;
return true;
}
if (DestRC == Mips::CPURegsRegisterClass)
@ -169,7 +170,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
else if (DestRC == Mips::AFGR64RegisterClass)
BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
else
assert (0 && "Can't copy this register");
// Can't copy this register
return false;
return true;
}
void MipsInstrInfo::

2
lib/Target/Mips/MipsInstrInfo.h
View File

@ -169,7 +169,7 @@ public:
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB,
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,

12
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -315,14 +315,14 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
return 2;
}
void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
cerr << "Not yet supported!";
abort();
// Not yet supported!
return false;
}
if (DestRC == PPC::GPRCRegisterClass) {
@ -340,9 +340,11 @@ void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
} else if (DestRC == PPC::CRBITRCRegisterClass) {
BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
cerr << "Attempt to copy register that is not GPR or FPR";
abort();
// Attempt to copy register that is not GPR or FPR
return false;
}
return true;
}
bool

2
lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -112,7 +112,7 @@ public:
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB,
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,

11
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -109,14 +109,14 @@ SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
return 1;
}
void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
cerr << "Not yet supported!";
abort();
// Not yet supported!
return false;
}
if (DestRC == SP::IntRegsRegisterClass)
@ -127,7 +127,10 @@ void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
.addReg(SrcReg);
else
assert (0 && "Can't copy this register");
// Can't copy this register
return false;
return true;
}
void SparcInstrInfo::

2
lib/Target/Sparc/SparcInstrInfo.h
View File

@ -68,7 +68,7 @@ public:
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB,
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,

32
lib/Target/X86/X86InstrInfo.cpp
View File

@ -1592,7 +1592,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
return 2;
}
void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
@ -1626,11 +1626,10 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
} else if (DestRC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64rr;
} else {
assert(0 && "Unknown regclass");
abort();
return false;
}
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
return;
return true;
}
// Moving EFLAGS to / from another register requires a push and a pop.
@ -1639,30 +1638,31 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
if (DestRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFQ));
BuildMI(MBB, MI, get(X86::POP64r), DestReg);
return;
return true;
} else if (DestRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFD));
BuildMI(MBB, MI, get(X86::POP32r), DestReg);
return;
return true;
}
} else if (DestRC == &X86::CCRRegClass) {
assert(DestReg == X86::EFLAGS);
if (SrcRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFQ));
return;
return true;
} else if (SrcRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFD));
return;
return true;
}
}
// Moving from ST(0) turns into FpGET_ST0_32 etc.
if (SrcRC == &X86::RSTRegClass) {
// Copying from ST(0)/ST(1).
assert((SrcReg == X86::ST0 || SrcReg == X86::ST1) &&
"Can only copy from ST(0)/ST(1) right now");
if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
// Can only copy from ST(0)/ST(1) right now
return false;
bool isST0 = SrcReg == X86::ST0;
unsigned Opc;
if (DestRC == &X86::RFP32RegClass)
@ -1674,13 +1674,15 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
}
BuildMI(MBB, MI, get(Opc), DestReg);
return;
return true;
}
// Moving to ST(0) turns into FpSET_ST0_32 etc.
if (DestRC == &X86::RSTRegClass) {
// Copying to ST(0). FIXME: handle ST(1) also
assert(DestReg == X86::ST0 && "Can only copy to TOS right now");
if (DestReg != X86::ST0)
// Can only copy to TOS right now
return false;
unsigned Opc;
if (SrcRC == &X86::RFP32RegClass)
Opc = X86::FpSET_ST0_32;
@ -1691,11 +1693,11 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
Opc = X86::FpSET_ST0_80;
}
BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
return;
return true;
}
assert(0 && "Not yet supported!");
abort();
// Not yet supported!
return false;
}
static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,

2
lib/Target/X86/X86InstrInfo.h
View File

@ -311,7 +311,7 @@ public:
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB,
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,