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Reuse the enum names from X86Desc in the X86Disassembler.
This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150303 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -19,5 +19,5 @@
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type = Library
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name = X86Disassembler
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parent = X86
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required_libraries = MC Support X86Info
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required_libraries = MC Support X86Desc X86Info
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add_to_library_groups = X86
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@ -21,6 +21,7 @@
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MemoryObject.h"
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@ -42,6 +43,11 @@ void x86DisassemblerDebug(const char *file,
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dbgs() << file << ":" << line << ": " << s;
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}
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const char *x86DisassemblerGetInstrName(unsigned Opcode, void *mii) {
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const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
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return MII->getName(Opcode);
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}
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#define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
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namespace llvm {
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@ -67,12 +73,13 @@ extern Target TheX86_32Target, TheX86_64Target;
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static bool translateInstruction(MCInst &target,
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InternalInstruction &source);
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X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode) :
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MCDisassembler(STI),
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fMode(mode) {
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}
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X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI,
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DisassemblerMode mode,
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const MCInstrInfo *MII)
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: MCDisassembler(STI), MII(MII), fMode(mode) {}
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X86GenericDisassembler::~X86GenericDisassembler() {
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delete MII;
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}
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EDInstInfo *X86GenericDisassembler::getEDInfo() const {
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@ -127,6 +134,7 @@ X86GenericDisassembler::getInstruction(MCInst &instr,
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(void*)®ion,
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loggerFn,
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(void*)&vStream,
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(void*)MII,
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address,
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fMode);
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@ -590,12 +598,16 @@ static bool translateInstruction(MCInst &mcInst,
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return false;
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}
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static MCDisassembler *createX86_32Disassembler(const Target &T, const MCSubtargetInfo &STI) {
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return new X86Disassembler::X86GenericDisassembler(STI, MODE_32BIT);
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static MCDisassembler *createX86_32Disassembler(const Target &T,
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const MCSubtargetInfo &STI) {
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return new X86Disassembler::X86GenericDisassembler(STI, MODE_32BIT,
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T.createMCInstrInfo());
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}
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static MCDisassembler *createX86_64Disassembler(const Target &T, const MCSubtargetInfo &STI) {
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return new X86Disassembler::X86GenericDisassembler(STI, MODE_64BIT);
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static MCDisassembler *createX86_64Disassembler(const Target &T,
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const MCSubtargetInfo &STI) {
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return new X86Disassembler::X86GenericDisassembler(STI, MODE_64BIT,
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T.createMCInstrInfo());
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}
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extern "C" void LLVMInitializeX86Disassembler() {
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@ -90,6 +90,7 @@
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namespace llvm {
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class MCInst;
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class MCInstrInfo;
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class MCSubtargetInfo;
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class MemoryObject;
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class raw_ostream;
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@ -102,11 +103,13 @@ namespace X86Disassembler {
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/// All each platform class should have to do is subclass the constructor, and
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/// provide a different disassemblerMode value.
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class X86GenericDisassembler : public MCDisassembler {
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const MCInstrInfo *MII;
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public:
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/// Constructor - Initializes the disassembler.
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///
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/// @param mode - The X86 architecture mode to decode for.
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X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode);
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X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode,
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const MCInstrInfo *MII);
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private:
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~X86GenericDisassembler();
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public:
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@ -712,7 +712,7 @@ static BOOL is16BitEquvalent(const char* orig, const char* equiv) {
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* @return - 0 if the ModR/M could be read when needed or was not needed;
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* nonzero otherwise.
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*/
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static int getID(struct InternalInstruction* insn) {
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static int getID(struct InternalInstruction* insn, void *miiArg) {
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uint8_t attrMask;
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uint16_t instructionID;
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@ -844,8 +844,12 @@ static int getID(struct InternalInstruction* insn) {
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}
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specWithOpsize = specifierForUID(instructionIDWithOpsize);
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if (is16BitEquvalent(spec->name, specWithOpsize->name)) {
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const char *specName = x86DisassemblerGetInstrName(instructionID, miiArg);
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const char *specWithOpSizeSizeName =
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x86DisassemblerGetInstrName(instructionIDWithOpsize, miiArg);
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if (is16BitEquvalent(specName, specWithOpSizeSizeName)) {
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insn->instructionID = instructionIDWithOpsize;
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insn->spec = specWithOpsize;
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} else {
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@ -1608,6 +1612,7 @@ int decodeInstruction(struct InternalInstruction* insn,
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void* readerArg,
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dlog_t logger,
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void* loggerArg,
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void* miiArg,
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uint64_t startLoc,
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DisassemblerMode mode) {
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memset(insn, 0, sizeof(struct InternalInstruction));
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@ -1623,7 +1628,7 @@ int decodeInstruction(struct InternalInstruction* insn,
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if (readPrefixes(insn) ||
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readOpcode(insn) ||
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getID(insn) ||
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getID(insn, miiArg) ||
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insn->instructionID == 0 ||
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readOperands(insn))
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return -1;
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@ -21,7 +21,6 @@ extern "C" {
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#endif
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#define INSTRUCTION_SPECIFIER_FIELDS \
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const char* name;
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#define INSTRUCTION_IDS \
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unsigned instructionIDs;
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@ -554,6 +553,7 @@ int decodeInstruction(struct InternalInstruction* insn,
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void* readerArg,
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dlog_t logger,
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void* loggerArg,
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void* miiArg,
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uint64_t startLoc,
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DisassemblerMode mode);
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@ -568,6 +568,8 @@ void x86DisassemblerDebug(const char *file,
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unsigned line,
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const char *s);
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const char *x86DisassemblerGetInstrName(unsigned Opcode, void *mii);
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#ifdef __cplusplus
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}
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#endif
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@ -486,7 +486,7 @@ void DisassemblerTables::emitInstructionInfo(raw_ostream &o, uint32_t &i)
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i--;
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o.indent(i * 2) << "}," << "\n";
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o.indent(i * 2) << "\"" << InstructionSpecifiers[index].name << "\"";
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o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
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o << "\n";
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i--;
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